diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v
index 54ed74b..2aa5b8a 100644
--- a/rtl/serv_decode.v
+++ b/rtl/serv_decode.v
@@ -15,7 +15,6 @@ module serv_decode
    output reg       o_ebreak,
    output reg       o_branch_op,
    output reg       o_shift_op,
-   output reg       o_slt_or_branch,
    output reg       o_rd_op,
    output reg       o_two_stage_op,
    output reg       o_dbus_en,
@@ -79,7 +78,6 @@ module serv_decode
 	~opcode[2] | (funct3[0] & ~funct3[1] & ~opcode[0] & ~opcode[4]) |
 	(funct3[1] & ~funct3[2] & ~opcode[0] & ~opcode[4]) | co_mdu_op;
    wire co_shift_op = (opcode[2] & ~funct3[1]) & !co_mdu_op;
-   wire co_slt_or_branch = (opcode[4] | (funct3[1] & opcode[2]) | (imm30 & opcode[2] & opcode[3] & ~funct3[2])) & !co_mdu_op;
    wire co_branch_op = opcode[4];
    wire co_dbus_en    = ~opcode[2] & ~opcode[4];
    wire co_mtval_pc   = opcode[4];
@@ -259,7 +257,6 @@ module serv_decode
             o_ebreak           = co_ebreak;
             o_branch_op        = co_branch_op;
             o_shift_op         = co_shift_op;
-            o_slt_or_branch    = co_slt_or_branch;
             o_rd_op            = co_rd_op;
             o_mdu_op           = co_mdu_op;
             o_ext_funct3       = co_ext_funct3;
@@ -321,7 +318,6 @@ module serv_decode
                o_mtval_pc         <= co_mtval_pc;
                o_branch_op        <= co_branch_op;
                o_shift_op         <= co_shift_op;
-               o_slt_or_branch    <= co_slt_or_branch;
                o_rd_op            <= co_rd_op;
                o_mdu_op           <= co_mdu_op;
                o_ext_funct3       <= co_ext_funct3;
diff --git a/rtl/serv_state.v b/rtl/serv_state.v
index 4e0f293..03b7684 100644
--- a/rtl/serv_state.v
+++ b/rtl/serv_state.v
@@ -40,7 +40,8 @@ module serv_state
    input wire 	     i_branch_op,
    input wire 	     i_shift_op,
    input wire 	     i_sh_right,
-   input wire 	     i_slt_or_branch,
+   input wire 	     i_alu_rd_sel1,
+   input wire 	     i_rd_alu_en,
    input wire 	     i_e_op,
    input wire 	     i_rd_op,
    //MDU
@@ -95,10 +96,14 @@ module serv_state
 
    //Prepare RF for writes when everything is ready to enter stage two
    // and the first stage didn't cause a misalign exception
-   assign o_rf_wreq = !misalign_trap_sync & !o_cnt_en & init_done &
-	   	      ((i_shift_op & (i_sh_done | !i_sh_right)) |
+   //Left shifts, SLT & Branch ops. First cycle after init
+   //Right shift. o_sh_done
+   //Mem ops. i_dbus_ack
+   //MDU ops. i_mdu_ready
+   assign o_rf_wreq = (i_shift_op & (i_sh_right ? (i_sh_done & !o_cnt_en & init_done) : stage_two_req)) |
 	   	       i_dbus_ack | (MDU & i_mdu_ready) |
-	   	       i_slt_or_branch);
+	   	      (i_branch_op & stage_two_req & !misalign_trap_sync) |
+	   	      (i_rd_alu_en & i_alu_rd_sel1 & stage_two_req);
 
    assign o_dbus_cyc = !o_cnt_en & init_done & i_dbus_en & !i_mem_misalign;
 
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index dafa15f..8bac6af 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -88,7 +88,6 @@ module serv_top
    wire 	 ebreak;
    wire 	 branch_op;
    wire 	 shift_op;
-   wire 	 slt_or_branch;
    wire 	 rd_op;
    wire   mdu_op;
 
@@ -267,7 +266,8 @@ module serv_top
       .i_branch_op    (branch_op),
       .i_shift_op     (shift_op),
       .i_sh_right     (sh_right),
-      .i_slt_or_branch (slt_or_branch),
+      .i_alu_rd_sel1  (alu_rd_sel[1]),
+      .i_rd_alu_en    (rd_alu_en),
       .i_e_op         (e_op),
       .i_rd_op        (rd_op),
       //MDU
@@ -303,7 +303,6 @@ module serv_top
       .o_ebreak           (ebreak),
       .o_branch_op        (branch_op),
       .o_shift_op         (shift_op),
-      .o_slt_or_branch    (slt_or_branch),
       .o_rd_op            (rd_op),
       .o_sh_right         (sh_right),
       .o_mdu_op           (mdu_op),