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Code Issues Releases Wiki Activity

Synthesis fixes

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This commit is contained in:
Olof Kindgren
2018-11-22 20:58:45 +01:00
parent 458d12c81d
commit 1bbf8e3ce9
11 changed files with 67 additions and 87 deletions
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38
bench/serv_arbiter.v
View File

@@ -1,26 +1,26 @@
module serv_arbiter
(
input i_ibus_active,
input [31:0] i_wb_cpu_dbus_adr,
input [31:0] i_wb_cpu_dbus_dat,
input [3:0] i_wb_cpu_dbus_sel,
input i_wb_cpu_dbus_we,
input i_wb_cpu_dbus_cyc,
output [31:0] o_wb_cpu_dbus_rdt,
output o_wb_cpu_dbus_ack,
input wire i_ibus_active,
input wire [31:0] i_wb_cpu_dbus_adr,
input wire [31:0] i_wb_cpu_dbus_dat,
input wire [3:0] i_wb_cpu_dbus_sel,
input wire i_wb_cpu_dbus_we,
input wire i_wb_cpu_dbus_cyc,
output wire [31:0] o_wb_cpu_dbus_rdt,
output wire o_wb_cpu_dbus_ack,
input [31:0] i_wb_cpu_ibus_adr,
input i_wb_cpu_ibus_cyc,
output [31:0] o_wb_cpu_ibus_rdt,
output o_wb_cpu_ibus_ack,
input wire [31:0] i_wb_cpu_ibus_adr,
input wire i_wb_cpu_ibus_cyc,
output wire [31:0] o_wb_cpu_ibus_rdt,
output wire o_wb_cpu_ibus_ack,
output [31:0] o_wb_cpu_adr,
output [31:0] o_wb_cpu_dat,
output [3:0] o_wb_cpu_sel,
output o_wb_cpu_we,
output o_wb_cpu_cyc,
input [31:0] i_wb_cpu_rdt,
input i_wb_cpu_ack);
output wire [31:0] o_wb_cpu_adr,
output wire [31:0] o_wb_cpu_dat,
output wire [3:0] o_wb_cpu_sel,
output wire o_wb_cpu_we,
output wire o_wb_cpu_cyc,
input wire [31:0] i_wb_cpu_rdt,
input wire i_wb_cpu_ack);
assign o_wb_cpu_dbus_rdt = i_wb_cpu_rdt;
assign o_wb_cpu_dbus_ack = i_wb_cpu_ack & !i_ibus_active;

42
bench/serv_mux.v
View File

@@ -6,30 +6,30 @@
*/
module serv_mux
(
input i_clk,
input i_rst,
input [31:0] i_wb_cpu_adr,
input [31:0] i_wb_cpu_dat,
input [3:0] i_wb_cpu_sel,
input i_wb_cpu_we,
input i_wb_cpu_cyc,
output [31:0] o_wb_cpu_rdt,
output reg o_wb_cpu_ack,
input wire i_clk,
input wire i_rst,
input wire [31:0] i_wb_cpu_adr,
input wire [31:0] i_wb_cpu_dat,
input wire [3:0] i_wb_cpu_sel,
input wire i_wb_cpu_we,
input wire i_wb_cpu_cyc,
output wire [31:0] o_wb_cpu_rdt,
output reg o_wb_cpu_ack,
output [31:0] o_wb_mem_adr,
output [31:0] o_wb_mem_dat,
output [3:0] o_wb_mem_sel,
output o_wb_mem_we,
output o_wb_mem_cyc,
input [31:0] i_wb_mem_rdt,
output wire [31:0] o_wb_mem_adr,
output wire [31:0] o_wb_mem_dat,
output wire [3:0] o_wb_mem_sel,
output wire o_wb_mem_we,
output wire o_wb_mem_cyc,
input wire [31:0] i_wb_mem_rdt,
output o_wb_gpio_dat,
output o_wb_gpio_cyc,
output wire o_wb_gpio_dat,
output wire o_wb_gpio_cyc,
output [31:0] o_wb_timer_dat,
output o_wb_timer_we,
output o_wb_timer_cyc,
input [31:0] i_wb_timer_rdt);
output wire [31:0] o_wb_timer_dat,
output wire o_wb_timer_we,
output wire o_wb_timer_cyc,
input wire [31:0] i_wb_timer_rdt);
parameter sim = 0;

8
bench/serv_wrapper.v
View File

@@ -131,16 +131,12 @@ serv_arbiter serv_arbiter
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_mem_adr[$clog2(MEMORY_SIZE)-1:0]),
.wb_stb_i (1'b1),
.wb_cyc_i (wb_mem_cyc),
.wb_cti_i (3'b000),
.wb_bte_i (2'b00),
.wb_we_i (wb_mem_we) ,
.wb_sel_i (wb_mem_sel),
.wb_dat_i (wb_mem_dat),
.wb_dat_o (wb_mem_rdt),
.wb_ack_o (),
.wb_err_o ());
.wb_ack_o ());
riscv_timer riscv_timer
(.i_clk (wb_clk),
@@ -165,7 +161,6 @@ serv_arbiter serv_arbiter
.o_ibus_adr (wb_cpu_ibus_adr),
.o_ibus_cyc (wb_cpu_ibus_cyc),
.o_ibus_stb (),
.i_ibus_rdt (wb_cpu_ibus_rdt),
.i_ibus_ack (wb_cpu_ibus_ack),
@@ -174,7 +169,6 @@ serv_arbiter serv_arbiter
.o_dbus_sel (wb_cpu_dbus_sel),
.o_dbus_we (wb_cpu_dbus_we),
.o_dbus_cyc (wb_cpu_dbus_cyc),
.o_dbus_stb (),
.i_dbus_rdt (wb_cpu_dbus_rdt),
.i_dbus_ack (wb_cpu_dbus_ack));