Synthesis fixes

rtl/serv_alu.v

@@ -33,6 +33,7 @@ module serv_alu
    reg         init_r;
    wire        shamt_l;
    wire        shamt_ser;
+   wire        plus_1;
 
    ser_add ser_add_inv_shamt_plus1
      (
@@ -63,7 +64,6 @@ module serv_alu
       .i_d (i_rs1),
       .o_q (result_sh));
 
-   wire       plus_1 = i_en & !en_r;
    wire       b_inv_plus_1;
 
    ser_add ser_add_inv_plus_1
@@ -107,7 +107,7 @@ module serv_alu
    reg last_eq;
 
    wire       result_lt2 = last_eq ? result_lt : msb_lt;
-
+   assign plus_1 = i_en & !en_r;
    assign o_cmp = i_cmp_neg^((i_cmp_sel == ALU_CMP_EQ) ? result_eq : result_lt2);
 
    assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add :

rtl/serv_decode.v

@@ -261,7 +261,7 @@ module serv_decode
    wire gate1  = (cnt == 0) & ((opcode == OP_BRANCH) | (opcode == OP_JAL));
    wire gate12 = (cnt < 12) & utype;
 
-   wire o_imm = (!(gate1 | gate12) & (cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]));
+   assign o_imm = (!(gate1 | gate12) & (cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]));
 
    assign o_op_b_source = (opcode == OP_OPIMM)  ? OP_B_SOURCE_IMM :
                           (opcode == OP_BRANCH) ? OP_B_SOURCE_RS2 :

rtl/serv_mem_if.v

@@ -20,12 +20,10 @@ module serv_mem_if
    output wire [3:0]  o_wb_sel,
    output wire 	      o_wb_we ,
    output reg 	      o_wb_cyc = 1'b0,
-   output wire 	      o_wb_stb,
    input wire [31:0]  i_wb_rdt,
    input wire 	      i_wb_ack);
 
    wire          wb_en = o_wb_cyc & i_wb_ack;
-   assign o_wb_stb = o_wb_cyc;
    reg           init_r;
    reg           en_r;
    reg           en_2r;

rtl/serv_regfile.v

@@ -16,6 +16,7 @@ module serv_regfile
 
    wire [31:0]  rs;
 
+   wire [4:0] 	raddr2 = raddr & {5{i_rs_en}};
    reg [31:0] mask;
 
    always @(i_rd_addr)
@@ -58,7 +59,6 @@ module serv_regfile
       if (i_rs_en)
         raddr <= raddr + 1;
    end
-   wire [4:0] raddr2 = raddr & {5{i_rs_en}};
 
    assign o_rs1 = (|i_rs1_addr) ? rs[i_rs1_addr] : 1'b0;
    assign o_rs2 = (|i_rs2_addr) ? rs[i_rs2_addr] : 1'b0;

rtl/serv_top.v

@@ -34,7 +34,6 @@ module serv_top
 `endif
    output wire [31:0] o_ibus_adr,
    output wire 	      o_ibus_cyc,
-   output wire 	      o_ibus_stb,
    input wire [31:0]  i_ibus_rdt,
    input wire 	      i_ibus_ack,
    output wire [31:0] o_dbus_adr,
@@ -42,12 +41,9 @@ module serv_top
    output wire [3:0]  o_dbus_sel,
    output wire 	      o_dbus_we ,
    output wire 	      o_dbus_cyc,
-   output wire 	      o_dbus_stb,
    input wire [31:0]  i_dbus_rdt,
    input wire 	      i_dbus_ack);
 
-   assign o_ibus_stb = o_ibus_cyc;
-
 `include "serv_params.vh"
 
    wire [4:0]    rd_addr;
@@ -190,7 +186,6 @@ module serv_top
       .o_ibus_cyc (o_ibus_cyc),
       .i_ibus_ack (i_ibus_ack));
 
-   //TODO: Pass imm through alu to avoid 5-way mux
    assign rd = (rd_source == RD_SOURCE_CTRL) ? ctrl_rd :
                (rd_source == RD_SOURCE_ALU)  ? alu_rd  :
                (rd_source == RD_SOURCE_MEM)  ? mem_rd  : csr_rd;
@@ -249,7 +244,6 @@ module serv_top
       .o_wb_sel   (o_dbus_sel),
       .o_wb_we    (o_dbus_we ),
       .o_wb_cyc   (o_dbus_cyc),
-      .o_wb_stb   (o_dbus_stb),
       .i_wb_rdt   (i_dbus_rdt),
       .i_wb_ack   (i_dbus_ack));
 

rtl/shift_reg.v

@@ -1,4 +1,5 @@
 module shift_reg
+  #(parameter LEN = 0)
   (
    input wire 		 clk,
    input wire 		 i_en,
@@ -6,7 +7,6 @@ module shift_reg
    output wire 		 o_q,
    output wire [LEN-2:0] o_par);
 
-   parameter LEN = 0;
    parameter INIT = 0;
 
    reg [LEN-1:0] 	 data = INIT;