diff --git a/rtl/serv_state.v b/rtl/serv_state.v
index b33606c..1886307 100644
--- a/rtl/serv_state.v
+++ b/rtl/serv_state.v
@@ -1,7 +1,7 @@
 module serv_state
   #(parameter RESET_STRATEGY = "MINI",
     parameter [0:0] WITH_CSR = 1,
-    parameter [0:0] COMPRESSED =0,
+    parameter [0:0] ALIGN =0,
     parameter [0:0] MDU = 0)
   (
    input wire 	     i_clk,
@@ -187,7 +187,7 @@ module serv_state
 
 	 //trap_pending is only guaranteed to have correct value during the
 	 // last cycle of the init stage
-	 wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !COMPRESSED) |
+	 wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) |
 					 (i_dbus_en   & i_mem_misalign));
 
 	 always @(posedge i_clk) begin
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index 1e66b38..b239706 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -224,7 +224,7 @@ module serv_top
      #(.RESET_STRATEGY (RESET_STRATEGY),
        .WITH_CSR (WITH_CSR),
        .MDU(MDU),
-       .COMPRESSED(COMPRESSED))
+       .ALIGN(ALIGN))
    state
      (
       .i_clk (clk),