diff --git a/rtl/serv_state.v b/rtl/serv_state.v
index 7eadd26..7fa088a 100644
--- a/rtl/serv_state.v
+++ b/rtl/serv_state.v
@@ -45,7 +45,7 @@ module serv_state
 
    reg 	stage_two_req;
    reg 	init_done;
-   reg 	misalign_trap_sync;
+   wire misalign_trap_sync;
 
    reg [4:2] o_cnt;
    reg [3:0] o_cnt_r;
@@ -169,6 +169,8 @@ module serv_state
 
    generate
       if (WITH_CSR) begin
+	 reg 	misalign_trap_sync_r;
+
 	 //trap_pending is only guaranteed to have correct value during the
 	 // last cycle of the init stage
 	 wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign) |
@@ -176,13 +178,13 @@ module serv_state
 
 	 always @(posedge i_clk) begin
 	    if (o_cnt_done)
-	      misalign_trap_sync <= trap_pending & o_init;
+	      misalign_trap_sync_r <= trap_pending & o_init;
 	    if (i_rst)
 	      if (RESET_STRATEGY != "NONE")
-		misalign_trap_sync <= 1'b0;
+		misalign_trap_sync_r <= 1'b0;
 	 end
+	 assign misalign_trap_sync = misalign_trap_sync_r;
       end else
-	always @(*)
-	  misalign_trap_sync = 1'b0;
+	assign misalign_trap_sync = 1'b0;
    endgenerate
 endmodule