diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v index 64634ae..e6d7a46 100644 --- a/rtl/serv_alu.v +++ b/rtl/serv_alu.v @@ -4,6 +4,7 @@ module serv_alu input wire clk, input wire i_rst, input wire i_en, + input wire i_cnt0, input wire i_rs1, input wire i_rs2, input wire i_imm, @@ -33,7 +34,6 @@ module serv_alu wire [4:0] shamt; reg shamt_msb; - reg en_r; wire shamt_ser; wire plus_1; @@ -82,7 +82,7 @@ module serv_alu assign result_eq = eq & eq_r; assign result_lt = eq ? lt_r : op_b^lt_sign; - assign plus_1 = i_en & !en_r; + assign plus_1 = i_cnt0; assign o_cmp = i_cmp_eq ? result_eq : result_lt; localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor @@ -104,7 +104,6 @@ module serv_alu result_lt_r <= result_lt; end eq_r <= result_eq | ~i_en; - en_r <= i_en; if (i_shamt_en) shamt_msb <= b_inv_plus_1_cy; diff --git a/rtl/serv_bufreg.v b/rtl/serv_bufreg.v index e9358fa..1f8c70c 100644 --- a/rtl/serv_bufreg.v +++ b/rtl/serv_bufreg.v @@ -1,8 +1,8 @@ module serv_bufreg ( input wire i_clk, - input wire [4:2] i_cnt, - input wire [1:0] i_cnt_r, + input wire i_cnt0, + input wire i_cnt1, input wire i_en, input wire i_init, input wire i_loop, @@ -19,7 +19,7 @@ module serv_bufreg reg c_r; reg [31:0] data; - wire clr_lsb = (i_cnt[4:2] == 3'd0) & i_cnt_r[0] & i_clr_lsb; + wire clr_lsb = i_cnt0 & i_clr_lsb; assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r; @@ -30,9 +30,9 @@ module serv_bufreg if (i_en) data <= {(i_loop & !i_init) ? o_q : q, data[31:1]}; - if ((i_cnt[4:2] == 3'd0) & i_cnt_r[0] & i_init) + if (i_cnt0 & i_init) o_lsb[0] <= q; - if ((i_cnt[4:2] == 3'd0) & i_cnt_r[1] & i_init) + if (i_cnt1 & i_init) o_lsb[1] <= q; end diff --git a/rtl/serv_csr.v b/rtl/serv_csr.v index 40423e1..897e272 100644 --- a/rtl/serv_csr.v +++ b/rtl/serv_csr.v @@ -3,8 +3,11 @@ module serv_csr ( input wire i_clk, input wire i_en, - input wire [4:2] i_cnt, - input wire [3:2] i_cnt_r, + input wire i_cnt0to3, + input wire i_cnt2, + input wire i_cnt3, + input wire i_cnt7, + input wire i_cnt_done, input wire i_e_op, input wire i_ebreak, input wire i_mem_cmd, @@ -56,8 +59,8 @@ module serv_csr wire timer_irq = i_mtip & mstatus_mie & mie_mtie; - assign mcause = (i_cnt[4:2] == 3'd0) ? mcause3_0[0] : //[3:0] - ((i_cnt[4:2] == 3'd7) & i_cnt_r[3]) ? mcause31 //[31] + assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0] + i_cnt_done ? mcause31 //[31] : 1'b0; assign o_csr_in = csr_in; @@ -70,13 +73,13 @@ module serv_csr Note: To save resources mstatus_mpie (mstatus bit 7) is not readable or writable from sw */ - if (i_mstatus_en & (i_cnt[4:2] == 3'd0) & i_cnt_r[3]) + if (i_mstatus_en & i_cnt3) mstatus_mie <= csr_in; - if (i_mie_en & (i_cnt[4:2] == 3'd1) & i_cnt_r[3]) + if (i_mie_en & i_cnt7) mie_mtie <= csr_in; - mstatus <= (i_cnt[4:2] == 0) & i_cnt_r[2] & mstatus_mie; + mstatus <= i_cnt2 & mstatus_mie; timer_irq_r <= timer_irq; @@ -95,9 +98,9 @@ module serv_csr end if (i_mcause_en & i_en) begin - if (i_cnt[4:2] == 3'd0) + if (i_cnt0to3) mcause3_0 <= {csr_in, mcause3_0[3:1]}; - if ((i_cnt[4:2] == 3'd7) & i_cnt_r[3]) + if (i_cnt_done) mcause31 <= csr_in; end end diff --git a/rtl/serv_ctrl.v b/rtl/serv_ctrl.v index 2ebd747..203c8a4 100644 --- a/rtl/serv_ctrl.v +++ b/rtl/serv_ctrl.v @@ -5,8 +5,8 @@ module serv_ctrl input wire i_rst, //State input wire i_pc_en, - input wire [4:2] i_cnt, - input wire [2:2] i_cnt_r, + input wire i_cnt12to31, + input wire i_cnt2, input wire i_cnt_done, //Control input wire i_jump, @@ -46,7 +46,7 @@ module serv_ctrl wire offset_a; wire offset_b; - assign plus_4 = i_cnt_r[2] & (i_cnt[4:2] == 3'd0); + assign plus_4 = i_cnt2; assign o_ibus_adr[0] = pc; assign o_bad_pc = pc_plus_offset_aligned; @@ -76,7 +76,7 @@ module serv_ctrl assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr); assign offset_a = i_pc_rel & pc; - assign offset_b = i_utype ? (i_imm & (i_cnt[4] | (i_cnt[3:2] == 2'b11))): i_buf; + assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf; assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r; assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r; diff --git a/rtl/serv_state.v b/rtl/serv_state.v index c2f9f76..b919264 100644 --- a/rtl/serv_state.v +++ b/rtl/serv_state.v @@ -20,8 +20,13 @@ module serv_state input wire i_rd_op, output reg o_init, output reg o_cnt_en, - output reg [4:0] o_cnt, - output reg [3:0] o_cnt_r, + output wire o_cnt0, + output wire o_cnt0to3, + output wire o_cnt12to31, + output wire o_cnt1, + output wire o_cnt2, + output wire o_cnt3, + output wire o_cnt7, output wire o_ctrl_pc_en, output reg o_ctrl_jump, output wire o_ctrl_trap, @@ -36,15 +41,31 @@ module serv_state parameter WITH_CSR = 1; + wire cnt4; + reg stage_two_req; + reg [4:2] o_cnt; + reg [3:0] o_cnt_r; + //Update PC in RUN or TRAP states assign o_ctrl_pc_en = o_cnt_en & !o_init; - assign o_alu_shamt_en = (o_cnt < 5) & o_init; assign o_mem_bytecnt = o_cnt[4:3]; + assign o_cnt0to3 = (o_cnt[4:2] == 3'd0); + assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11)); + assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0]; + assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1]; + assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2]; + assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3]; + assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0]; + assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3]; + + assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init; + + //slt*, branch/jump, shift, load/store wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op; @@ -90,12 +111,12 @@ module serv_state if (o_cnt_done) o_cnt_en <= 1'b0; - o_cnt <= o_cnt + {4'd0,o_cnt_en}; + o_cnt <= o_cnt + {2'd0,o_cnt_r[3]}; if (o_cnt_en) o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]}; if (i_rst) begin - o_cnt <= 5'd0; + o_cnt <= 3'd0; stage_two_pending <= 1'b0; o_ctrl_jump <= 1'b0; o_cnt_r <= 4'b0001; diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 0463568..70b4c46 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -88,8 +88,13 @@ module serv_top wire init; wire cnt_en; - wire [4:0] cnt; - wire [3:0] cnt_r; + wire cnt0to3; + wire cnt12to31; + wire cnt0; + wire cnt1; + wire cnt2; + wire cnt3; + wire cnt7; wire cnt_done; @@ -167,8 +172,13 @@ module serv_top .i_rd_op (rd_op), .o_init (init), .o_cnt_en (cnt_en), - .o_cnt (cnt), - .o_cnt_r (cnt_r), + .o_cnt0to3 (cnt0to3), + .o_cnt12to31 (cnt12to31), + .o_cnt0 (cnt0), + .o_cnt1 (cnt1), + .o_cnt2 (cnt2), + .o_cnt3 (cnt3), + .o_cnt7 (cnt7), .o_cnt_done (cnt_done), .o_bufreg_hold (bufreg_hold), .o_ctrl_pc_en (ctrl_pc_en), @@ -246,8 +256,8 @@ module serv_top serv_bufreg bufreg ( .i_clk (clk), - .i_cnt (cnt[4:2]), - .i_cnt_r (cnt_r[1:0]), + .i_cnt0 (cnt0), + .i_cnt1 (cnt1), .i_en (!bufreg_hold), .i_init (init), .i_loop (bufreg_loop), @@ -269,8 +279,8 @@ module serv_top .i_rst (i_rst), //State .i_pc_en (ctrl_pc_en), - .i_cnt (cnt[4:2]), - .i_cnt_r (cnt_r[2]), + .i_cnt12to31 (cnt12to31), + .i_cnt2 (cnt2), .i_cnt_done (cnt_done), //Control .i_jump (jump), @@ -295,6 +305,7 @@ module serv_top .clk (clk), .i_rst (i_rst), .i_en (cnt_en), + .i_cnt0 (cnt0), .i_rs1 (rs1), .i_rs2 (rs2), .i_imm (imm), @@ -392,8 +403,11 @@ module serv_top ( .i_clk (clk), .i_en (cnt_en), - .i_cnt (cnt[4:2]), - .i_cnt_r (cnt_r[3:2]), + .i_cnt0to3 (cnt0to3), + .i_cnt2 (cnt2), + .i_cnt3 (cnt3), + .i_cnt7 (cnt7), + .i_cnt_done (cnt_done), .i_e_op (e_op), .i_ebreak (ebreak), .i_mem_cmd (o_dbus_we),