From 2a76adc8dbf952c7961e3a3b82128f6c886a9f50 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Wed, 6 May 2020 20:07:29 +0200
Subject: [PATCH] Add compatibility with Xilinx ISE

---
 rtl/serv_rf_ram_if.v  | 5 ++---
 rtl/serv_rf_top.v     | 4 ++--
 servant/servant_ram.v | 2 ++
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/rtl/serv_rf_ram_if.v b/rtl/serv_rf_ram_if.v
index a0744ec..64da74c 100644
--- a/rtl/serv_rf_ram_if.v
+++ b/rtl/serv_rf_ram_if.v
@@ -2,7 +2,8 @@
 module serv_rf_ram_if
   #(parameter width=8,
     parameter csr_regs=4,
-    parameter depth=32*(32+csr_regs)/width)
+    parameter depth=32*(32+csr_regs)/width,
+    parameter l2w = $clog2(width))
   (
    //SERV side
    input wire 				i_clk,
@@ -27,8 +28,6 @@ module serv_rf_ram_if
    output wire [$clog2(depth)-1:0] 	o_raddr,
    input wire [width-1:0] 		i_rdata);
 
-   localparam l2w = $clog2(width);
-
    reg 				   rgnt;
    assign o_ready = rgnt | i_wreq;
 
diff --git a/rtl/serv_rf_top.v b/rtl/serv_rf_top.v
index 66aec5d..de00d38 100644
--- a/rtl/serv_rf_top.v
+++ b/rtl/serv_rf_top.v
@@ -3,7 +3,8 @@
 module serv_rf_top
   #(parameter RESET_PC = 32'd0,
     parameter WITH_CSR = 1,
-    parameter RF_WIDTH = 2)
+    parameter RF_WIDTH = 2,
+	parameter RF_L2D   = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
   (
    input wire 	      clk,
    input wire 	      i_rst,
@@ -44,7 +45,6 @@ module serv_rf_top
    input wire 	      i_dbus_ack);
 
    localparam CSR_REGS = WITH_CSR*4;
-   localparam RF_L2D = $clog2((32+CSR_REGS)*32/RF_WIDTH);
 
    wire 	      rf_wreq;
    wire 	      rf_rreq;
diff --git a/servant/servant_ram.v b/servant/servant_ram.v
index 11e058c..91340f1 100644
--- a/servant/servant_ram.v
+++ b/servant/servant_ram.v
@@ -32,7 +32,9 @@ module servant_ram
 
    initial
      if(|memfile) begin
+`ifndef ISE
 	$display("Preloading %m from %s", memfile);
+`endif
 	$readmemh(memfile, mem);
      end