diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v
index 6877596..e26a22b 100644
--- a/rtl/serv_decode.v
+++ b/rtl/serv_decode.v
@@ -55,8 +55,7 @@ module serv_decode
    output wire 	     o_imm,
    output wire 	     o_op_b_source,
    output wire 	     o_rd_csr_en,
-   output wire 	     o_rd_alu_en,
-   output wire 	     o_rd_mem_en);
+   output wire 	     o_rd_alu_en);
 
 `include "serv_params.vh"
 
@@ -226,7 +225,6 @@ module serv_decode
    assign o_op_b_source = opcode[3];
 
    assign o_rd_alu_en  = !opcode[0] & opcode[2] & !opcode[4];
-   assign o_rd_mem_en =              !opcode[2] & !opcode[4];
 
 
 endmodule
diff --git a/rtl/serv_mem_if.v b/rtl/serv_mem_if.v
index 789e848..9f93925 100644
--- a/rtl/serv_mem_if.v
+++ b/rtl/serv_mem_if.v
@@ -39,7 +39,7 @@ module serv_mem_if
 		 (dat_sel == 1) ? dat1[0] : dat0[0];
 
    wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]);
-   assign o_rd = dat_valid ? dat_cur : signbit & i_signed;
+   assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed);
 
 
    wire       upper_half = i_lsb[1];
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index d1256f4..091ac2d 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -55,7 +55,6 @@ module serv_top
    wire 	 slt_op;
 
    wire 	 rd_alu_en;
-   wire 	 rd_mem_en;
    wire 	 rd_csr_en;
    wire          ctrl_rd;
    wire          alu_rd;
@@ -231,8 +230,7 @@ module serv_top
       .o_imm              (imm),
       .o_op_b_source      (op_b_source),
       .o_rd_csr_en        (rd_csr_en),
-      .o_rd_alu_en        (rd_alu_en),
-      .o_rd_mem_en        (rd_mem_en));
+      .o_rd_alu_en        (rd_alu_en));
 
    assign o_dbus_adr = {bufreg_out[31:2], 2'b00};
 
@@ -284,7 +282,7 @@ module serv_top
    assign rd = (ctrl_rd ) |
 	       (rd_alu_en  & alu_rd ) |
 	       (csr_rd & rd_csr_en) |
-	       (rd_mem_en  & mem_rd);
+	       (mem_rd);
 
    assign op_b = (op_b_source == OP_B_SOURCE_IMM) ? imm : rs2;