diff --git a/README.md b/README.md
index 2307ede..cd6f750 100644
--- a/README.md
+++ b/README.md
@@ -76,23 +76,25 @@ Other applications can be tested by compiling and converting to bin and then hex
 
 ## Run RISC-V compliance tests
 
-**Note:** The following instructions are valid for version 1.0 of the RISC-V compliance tests. The target-specific support for SERV has not yet been ported to newer versions.
-
 Build the verilator model (if not already done)
 
-    fusesoc run --target=verilator_tb --build servant
+    fusesoc run --target=verilator_tb --build servant --memsize=8388608
+
+To build the verilator model with MDU (for M extension compliance tests):
+
+    fusesoc run --target=verilator_tb --flag=mdu --build servant --memsize=8388608
 
 Download the tests repo
 
-    git clone https://github.com/riscv/riscv-compliance --branch 1.0
+    git clone https://github.com/riscv-non-isa/riscv-arch-test.git
 
 To run the RISC-V compliance tests, we need to supply the SERV-specific support files and point the test suite to where it can find a target to run (i.e. the previously built Verilator model)
 
 Run the compliance tests
 
-    cd riscv-compliance && make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$WORKSPACE/build/servant_1.1.0/verilator_tb-verilator/Vservant_sim
+    cd riscv-arch-test && make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=I TARGET_SIM=$WORKSPACE/build/servant_1.1.0/verilator_tb-verilator/Vservant_sim
 
-The above will run all tests in the rv32i test suite. Since SERV also implement the `rv32im`, `rv32Zicsr` and `rv32Zifencei` extensions, these can also be tested by choosing any of them instead of rv32i as the `RISCV_ISA` variable.
+The above will run all tests in the rv32i test suite. Since SERV also implement the `M`, `privilege` and `Zifencei` extensions, these can also be tested by choosing any of them instead of `I` as the `RISCV_DEVICE` variable.
 
 ## Run on hardware
 
diff --git a/riscv-target/serv/compliance_io.h b/riscv-target/serv/compliance_io.h
deleted file mode 100644
index 5bfa263..0000000
--- a/riscv-target/serv/compliance_io.h
+++ /dev/null
@@ -1,36 +0,0 @@
-// RISC-V Compliance IO Test Header File
-
-/*
- * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
- * either express or implied.
- *
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-#ifndef _COMPLIANCE_IO_H
-#define _COMPLIANCE_IO_H
-
-//-----------------------------------------------------------------------
-// RV IO Macros (Non functional)
-//-----------------------------------------------------------------------
-
-#define RVTEST_IO_INIT
-#define RVTEST_IO_WRITE_STR(_SP, _STR)
-#define RVTEST_IO_CHECK()
-#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
-#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
-#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
-
-#endif // _COMPLIANCE_IO_H
diff --git a/riscv-target/serv/compliance_test.h b/riscv-target/serv/compliance_test.h
deleted file mode 100644
index 512793b..0000000
--- a/riscv-target/serv/compliance_test.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// RISC-V Compliance Test Header File
-// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
-// See LICENSE for license details.
-//
-// Description: Common header file for RV32I tests
-
-#ifndef _COMPLIANCE_TEST_H
-#define _COMPLIANCE_TEST_H
-
-//-----------------------------------------------------------------------
-// RV Compliance Macros
-//-----------------------------------------------------------------------
-
-#define RV_COMPLIANCE_HALT              \
-la a0, data_begin;	 \
-        la a1, data_end; \
-        li a2, 0x80000000; \
-complience_halt_loop: \
-        beq a0, a1, complience_halt_break; \
-        addi a3, a0, 4; \
-complience_halt_loop2: \
-        addi a3, a3, -1; \
-	\
-        lb a4, 0 (a3); \
-        srai a5, a4, 4; \
-        andi a5, a5, 0xF; \
-        li a6, 10; \
-        blt a5, a6, notLetter; \
-        addi a5, a5, 39; \
-notLetter: \
-        addi a5, a5, 0x30; \
-        sw a5, 0 (a2); \
-	\
-        srai a5, a4, 0; \
-        andi a5, a5, 0xF; \
-        li a6, 10; \
-        blt a5, a6, notLetter2; \
-        addi a5, a5, 39; \
-notLetter2: \
-        addi a5, a5, 0x30; \
-        sw a5, 0 (a2); \
-        bne a0, a3,complience_halt_loop2;  \
-        addi a0, a0, 4; \
-	\
-        li a4, '\n'; \
-        sw a4, 0 (a2); \
-        j complience_halt_loop; \
-  j complience_halt_break;		\
-complience_halt_break:; \
-	lui	a0,0x90000000>>12;	\
-	sw	a3,0(a0);		
-
-#define RV_COMPLIANCE_RV32M
-
-#define RV_COMPLIANCE_CODE_BEGIN                                              \
-        .section .text.init;                                            \
-        .align  4;                                                      \
-        .globl _start;                                                  \
-_start:                                                                 \
-
-#define RV_COMPLIANCE_CODE_END
-
-#define RV_COMPLIANCE_DATA_BEGIN .align 4; .global data_begin; data_begin:
-
-#define RV_COMPLIANCE_DATA_END .align 4; .global data_end; data_end:
-
-#endif
diff --git a/riscv-target/serv/device/rv32i/Makefile.include b/riscv-target/serv/device/rv32i_m/I/Makefile.include
similarity index 87%
rename from riscv-target/serv/device/rv32i/Makefile.include
rename to riscv-target/serv/device/rv32i_m/I/Makefile.include
index 046cff8..ed46241 100644
--- a/riscv-target/serv/device/rv32i/Makefile.include
+++ b/riscv-target/serv/device/rv32i_m/I/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) \
-        +timeout=100000000 \
+        +timeout=100000000000 \
         +signature=$(*).signature.output \
         +firmware=$(<).hex 2> $@
 
@@ -23,4 +23,4 @@ COMPILE_TARGET=\
 		-o $$@; \
 	$$(RISCV_OBJCOPY) -O binary $$@  $$@.bin; \
 	$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
-	python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 2048 > $$@.hex;
+	python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
diff --git a/riscv-target/serv/device/rv32i_m/M/Makefile.include b/riscv-target/serv/device/rv32i_m/M/Makefile.include
new file mode 100644
index 0000000..ed46241
--- /dev/null
+++ b/riscv-target/serv/device/rv32i_m/M/Makefile.include
@@ -0,0 +1,26 @@
+TARGET_SIM ?= server
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_TARGET=\
+    $(TARGET_SIM) \
+        +timeout=100000000000 \
+        +signature=$(*).signature.output \
+        +firmware=$(<).hex 2> $@
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+	$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+		-I$(ROOTDIR)/riscv-test-env/ \
+		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+		-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
+		-o $$@; \
+	$$(RISCV_OBJCOPY) -O binary $$@  $$@.bin; \
+	$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
+	python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
diff --git a/riscv-target/serv/device/rv32i_m/Zifencei/Makefile.include b/riscv-target/serv/device/rv32i_m/Zifencei/Makefile.include
new file mode 100644
index 0000000..ed46241
--- /dev/null
+++ b/riscv-target/serv/device/rv32i_m/Zifencei/Makefile.include
@@ -0,0 +1,26 @@
+TARGET_SIM ?= server
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_TARGET=\
+    $(TARGET_SIM) \
+        +timeout=100000000000 \
+        +signature=$(*).signature.output \
+        +firmware=$(<).hex 2> $@
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+	$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+		-I$(ROOTDIR)/riscv-test-env/ \
+		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+		-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
+		-o $$@; \
+	$$(RISCV_OBJCOPY) -O binary $$@  $$@.bin; \
+	$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
+	python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
diff --git a/riscv-target/serv/device/rv32i_m/privilege/Makefile.include b/riscv-target/serv/device/rv32i_m/privilege/Makefile.include
new file mode 100644
index 0000000..ed46241
--- /dev/null
+++ b/riscv-target/serv/device/rv32i_m/privilege/Makefile.include
@@ -0,0 +1,26 @@
+TARGET_SIM ?= server
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_TARGET=\
+    $(TARGET_SIM) \
+        +timeout=100000000000 \
+        +signature=$(*).signature.output \
+        +firmware=$(<).hex 2> $@
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+	$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+		-I$(ROOTDIR)/riscv-test-env/ \
+		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+		-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
+		-o $$@; \
+	$$(RISCV_OBJCOPY) -O binary $$@  $$@.bin; \
+	$$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \
+	python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin 524288 > $$@.hex;
diff --git a/riscv-target/serv/model_test.h b/riscv-target/serv/model_test.h
new file mode 100644
index 0000000..2b74203
--- /dev/null
+++ b/riscv-target/serv/model_test.h
@@ -0,0 +1,71 @@
+#ifndef _COMPLIANCE_MODEL_H
+#define _COMPLIANCE_MODEL_H
+
+#define RVMODEL_HALT                                              \
+    la a0, begin_signature;	 \
+    la a1, end_signature; \
+    li a2, 0x80000000; \
+    complience_halt_loop: \
+        beq a0, a1, complience_halt_break; \
+        addi a3, a0, 4; \
+    complience_halt_loop2: \
+        addi a3, a3, -1; \
+    \
+        lb a4, 0 (a3); \
+        srai a5, a4, 4; \
+        andi a5, a5, 0xF; \
+        li a6, 10; \
+        blt a5, a6, notLetter; \
+        addi a5, a5, 39; \
+    notLetter: \
+        addi a5, a5, 0x30; \
+        sw a5, 0 (a2); \
+    \
+        srai a5, a4, 0; \
+        andi a5, a5, 0xF; \
+        li a6, 10; \
+        blt a5, a6, notLetter2; \
+        addi a5, a5, 39; \
+    notLetter2: \
+        addi a5, a5, 0x30; \
+        sw a5, 0 (a2); \
+        bne a0, a3,complience_halt_loop2;  \
+        addi a0, a0, 4; \
+    \
+        li a4, '\n'; \
+        sw a4, 0 (a2); \
+        j complience_halt_loop; \
+        j complience_halt_break;		\
+    complience_halt_break:; \
+        lui	a0,0x90000000>>12;	\
+        sw	a3,0(a0);
+
+
+#define RVMODEL_DATA_BEGIN                                              \
+    .align 4; .global begin_signature; begin_signature: \
+
+#define RVMODEL_DATA_END                                                      \
+    .align 4; .global end_signature; end_signature:   \
+
+
+#define RVMODEL_BOOT \
+.section .text.init;                                            \
+        .align  4;                                                      \
+        .globl _start;                                                  \
+_start:  
+
+
+#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
+#define RVMODEL_IO_WRITE_STR(_SP, _STR)
+#define LOCAL_IO_PUSH(_SP)
+#define LOCAL_IO_POP(_SP)
+#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#define RVMODEL_SET_MSW_INT
+#define RVMODEL_CLEAR_MSW_INT
+#define RVMODEL_CLEAR_MTIMER_INT
+#define RVMODEL_CLEAR_MEXT_INT
+
+#endif // _COMPLIANCE_MODEL_H
\ No newline at end of file