diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v
index a93c516..2679a4a 100644
--- a/rtl/serv_alu.v
+++ b/rtl/serv_alu.v
@@ -1,5 +1,9 @@
 `default_nettype none
 module serv_alu
+  #(
+   parameter W = 1,
+   parameter B = W-1
+  )
   (
    input wire 	    clk,
    //State
@@ -13,29 +17,30 @@ module serv_alu
    input wire 	    i_cmp_sig,
    input wire [2:0] i_rd_sel,
    //Data
-   input wire 	    i_rs1,
-   input wire 	    i_op_b,
-   input wire 	    i_buf,
-   output wire 	    o_rd);
+   input wire  [B:0] i_rs1,
+   input wire  [B:0] i_op_b,
+   input wire  [B:0] i_buf,
+   output wire [B:0] o_rd);
 
-   wire        result_add;
+   wire [B:0]  result_add;
+   wire [B:0]  result_slt;
 
    reg 	       cmp_r;
 
    wire        add_cy;
-   reg 	       add_cy_r;
+   reg [B:0]   add_cy_r;
 
    //Sign-extended operands
-   wire rs1_sx  = i_rs1 & i_cmp_sig;
-   wire op_b_sx = i_op_b  & i_cmp_sig;
+   wire rs1_sx  = i_rs1[B] & i_cmp_sig;
+   wire op_b_sx = i_op_b[B]  & i_cmp_sig;
 
-   wire add_b = i_op_b^i_sub;
+   wire [B:0] add_b = i_op_b^{W{i_sub}};
 
    assign {add_cy,result_add}   = i_rs1+add_b+add_cy_r;
 
    wire result_lt = rs1_sx + ~op_b_sx + add_cy;
 
-   wire result_eq = !result_add & (cmp_r | i_cnt0);
+   wire result_eq = !(|result_add) & (cmp_r | i_cnt0);
 
    assign o_cmp = i_cmp_eq ? result_eq : result_lt;
 
@@ -51,15 +56,21 @@ module serv_alu
     i_bool_op will be 01 during shift operations, so by outputting zero under
     this condition we can safely or result_bool with i_buf
     */
-   wire result_bool = ((i_rs1 ^ i_op_b) & ~ i_bool_op[0]) | (i_bool_op[1] & i_op_b & i_rs1);
+   wire [B:0] result_bool = ((i_rs1 ^ i_op_b) & ~{W{i_bool_op[0]}}) | ({W{i_bool_op[1]}} & i_op_b & i_rs1);
+
+   assign result_slt[0] = cmp_r & i_cnt0;
+   generate
+      if (W>1) assign result_slt[B:1] = '0;
+   endgenerate
 
    assign o_rd = i_buf |
-                 (i_rd_sel[0] & result_add) |
-                 (i_rd_sel[1] & cmp_r & i_cnt0) |
-                 (i_rd_sel[2] & result_bool);
+                 ({W{i_rd_sel[0]}} & result_add) |
+                 ({W{i_rd_sel[1]}} & result_slt) |
+                 ({W{i_rd_sel[2]}} & result_bool);
 
    always @(posedge clk) begin
-      add_cy_r <= i_en ? add_cy : i_sub;
+      add_cy_r    <= {W{1'b0}};
+      add_cy_r[0] <= i_en ? add_cy : i_sub;
 
       if (i_en)
 	cmp_r <= o_cmp;