From 3179cfb107a10184e7f116f6c33b1d58f8273833 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Tue, 3 Dec 2019 10:28:27 +0100
Subject: [PATCH] Optimize alu eq_r and lt_r

---
 rtl/serv_alu.v | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v
index 842c9a2..8a1261b 100644
--- a/rtl/serv_alu.v
+++ b/rtl/serv_alu.v
@@ -93,7 +93,7 @@ module serv_alu
       .i_clk (clk),
       .i_a   (i_rs1),
       .i_b   (i_op_b),
-      .i_clr (!i_init),
+      .i_clr (!i_en),
       .i_sign (i_cnt_done & !i_cmp_uns),
       .o_q   (result_lt));
 
@@ -112,12 +112,10 @@ module serv_alu
    reg 	eq_r;
 
    always @(posedge clk) begin
-      if (i_init) begin
+      if (i_en) begin
 	 result_lt_r <= result_lt;
-	 eq_r <= result_eq;
-      end else begin
-	 eq_r <= 1'b1;
       end
+      eq_r <= result_eq | ~i_en;
       en_r <= i_en;
    end