From 3971ca942ed5c9a04384c67994b032006f522b0d Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 27 Aug 2021 12:18:54 +0200 Subject: [PATCH] Fix up RVFI --- rtl/serv_top.v | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 476e7ec..1866fb5 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -502,12 +502,18 @@ module serv_top wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en; always @(posedge clk) begin + /* End of instruction */ rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst; rvfi_order <= rvfi_order + {63'd0,rvfi_valid}; + + /* Get instruction word when it's fetched from ibus */ if (o_ibus_cyc & i_ibus_ack) rvfi_insn <= i_ibus_rdt; + + /* Store data written to rd */ if (o_wen0) rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]}; + if (cnt_done & ctrl_pc_en) begin rvfi_pc_rdata <= pc; if (!(rd_en & (|rd_addr))) begin @@ -521,18 +527,22 @@ module serv_top pc <= rvfi_pc_wdata; end + /* Not used */ rvfi_halt <= 1'b0; rvfi_intr <= 1'b0; rvfi_mode <= 2'd3; rvfi_ixl = 2'd1; + + /* RS1 not valid during J, U instructions (immdec_en[1]) */ + /* RS2 not valid during I, J, U instructions (immdec_en[2]) */ if (i_rf_ready) begin - rvfi_rs1_addr <= rs1_addr; - rvfi_rs2_addr <= rs2_addr; + rvfi_rs1_addr <= !immdec_en[1] ? rs1_addr : 5'd0; + rvfi_rs2_addr <= !immdec_en[2] /*rs2_valid*/ ? rs2_addr : 5'd0; rvfi_rd_addr <= rd_addr; end if (rs_en) begin - rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]}; - rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]}; + rvfi_rs1_rdata <= {!immdec_en[1] & rs1,rvfi_rs1_rdata[31:1]}; + rvfi_rs2_rdata <= {!immdec_en[2] & rs2,rvfi_rs2_rdata[31:1]}; end if (i_dbus_ack) begin