diff --git a/rtl/serv_state.v b/rtl/serv_state.v
index d1a1456..e12c112 100644
--- a/rtl/serv_state.v
+++ b/rtl/serv_state.v
@@ -3,6 +3,7 @@ module serv_state
    input wire 	     i_clk,
    input wire 	     i_rst,
    input wire 	     i_new_irq,
+   input wire 	     i_dbus_ack,
    input wire 	     i_rf_ready,
    input wire 	     i_take_branch,
    input wire 	     i_branch_op,
@@ -102,7 +103,7 @@ module serv_state
 
       case (state)
         IDLE : begin
-           if (i_rf_ready) begin
+           if (i_rf_ready | i_dbus_ack) begin
 	      state <= RUN;
               if (two_stage_op & !stage_two_pending)
 		state <= INIT;
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index 9a2a873..84e7a18 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -140,7 +140,8 @@ module serv_top
       .i_clk (clk),
       .i_rst          (i_rst),
       .i_new_irq      (new_irq),
-      .i_rf_ready     (rf_ready | i_dbus_ack),
+      .i_dbus_ack     (i_dbus_ack),
+      .i_rf_ready     (rf_ready),
       .i_take_branch  (take_branch),
       .i_branch_op    (branch_op),
       .i_mem_op       (mem_op),