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https://github.com/olofk/serv.git
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Update Compliance testing framework
This commit is contained in:
committed by
Olof Kindgren
parent
1bdd42acb5
commit
41ae06f6cf
18
verif/plugin-serv/env/link.ld
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18
verif/plugin-serv/env/link.ld
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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.text.init : { *(.text.init) }
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. = ALIGN(0x1000);
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.tohost : { *(.tohost) }
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. = ALIGN(0x1000);
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.text : { *(.text) }
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. = ALIGN(0x1000);
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.data : { *(.data) }
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.data.string : { *(.data.string)}
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.bss : { *(.bss) }
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_end = .;
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}
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71
verif/plugin-serv/env/model_test.h
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71
verif/plugin-serv/env/model_test.h
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#ifndef _COMPLIANCE_MODEL_H
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#define _COMPLIANCE_MODEL_H
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#define RVMODEL_HALT \
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la a0, begin_signature; \
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la a1, end_signature; \
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li a2, 0x80000000; \
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complience_halt_loop: \
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beq a0, a1, complience_halt_break; \
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addi a3, a0, 4; \
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complience_halt_loop2: \
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addi a3, a3, -1; \
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\
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lb a4, 0 (a3); \
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srai a5, a4, 4; \
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andi a5, a5, 0xF; \
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li a6, 10; \
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blt a5, a6, notLetter; \
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addi a5, a5, 39; \
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notLetter: \
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addi a5, a5, 0x30; \
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sw a5, 0 (a2); \
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\
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srai a5, a4, 0; \
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andi a5, a5, 0xF; \
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li a6, 10; \
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blt a5, a6, notLetter2; \
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addi a5, a5, 39; \
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notLetter2: \
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addi a5, a5, 0x30; \
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sw a5, 0 (a2); \
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bne a0, a3,complience_halt_loop2; \
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addi a0, a0, 4; \
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\
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li a4, '\n'; \
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sw a4, 0 (a2); \
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j complience_halt_loop; \
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j complience_halt_break; \
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complience_halt_break:; \
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lui a0,0x90000000>>12; \
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sw a3,0(a0);
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#define RVMODEL_DATA_BEGIN \
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.align 4; .global begin_signature; begin_signature: \
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#define RVMODEL_DATA_END \
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.align 4; .global end_signature; end_signature: \
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#define RVMODEL_BOOT \
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.section .text.init; \
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.align 4; \
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.globl _start; \
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_start:
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#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
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#define RVMODEL_IO_WRITE_STR(_SP, _STR)
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#define LOCAL_IO_PUSH(_SP)
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#define LOCAL_IO_POP(_SP)
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#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
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#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
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#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
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#define RVMODEL_SET_MSW_INT
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#define RVMODEL_CLEAR_MSW_INT
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#define RVMODEL_CLEAR_MTIMER_INT
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#define RVMODEL_CLEAR_MEXT_INT
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#endif // _COMPLIANCE_MODEL_H
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92
verif/plugin-serv/riscof_serv.py
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92
verif/plugin-serv/riscof_serv.py
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import os
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import logging
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import riscof.utils as utils
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from riscof.pluginTemplate import pluginTemplate
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logger = logging.getLogger()
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class serv(pluginTemplate):
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__model__ = "serv"
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__version__ = "1.2.0"
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def __init__(self, *args, **kwargs):
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sclass = super().__init__(*args, **kwargs)
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config = kwargs.get('config')
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if config is None:
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print("Please enter input file paths in configuration.")
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raise SystemExit(1)
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self.dut_exe = os.path.join(config['PATH'] if 'PATH' in config else "","serv")
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self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)
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self.pluginpath=os.path.abspath(config['pluginpath'])
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self.isa_spec = os.path.abspath(config['ispec'])
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self.platform_spec = os.path.abspath(config['pspec'])
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if 'target_run' in config and config['target_run']=='0':
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self.target_run = False
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else:
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self.target_run = True
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return sclass
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def initialise(self, suite, work_dir, archtest_env):
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self.work_dir = work_dir
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self.suite_dir = suite
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self.compile_cmd = 'riscv64-unknown-elf-gcc -march={0} \
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-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\
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-T '+self.pluginpath+'/env/link.ld\
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-I '+self.pluginpath+'/env/\
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-I ' + archtest_env + ' {1} -o {2} {3}'
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self.objcopy_cmd = 'riscv64-unknown-elf-objcopy -O binary {0} {1}.bin'
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self.objdump_cmd = 'riscv64-unknown-elf-objdump -D {0} > {1}.disass'
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self.hexgen_cmd = 'python3 makehex.py {0}/{1}.bin > {0}/{1}.hex'
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build_serv = 'cd $WORKSPACE \n \
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fusesoc library add mdu https://github.com/zeeshanrafique23/mdu\n'
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build_serv = build_serv + 'fusesoc run --target=verilator_tb --flag=mdu\
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--build --build-root=servant_test servant\
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--memsize=8388608 --compressed=1'
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utils.shellCommand(build_serv).run()
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self.sigdump_cmd = 'cd $WORKSPACE/servant_test/verilator_tb-verilator \n\
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./Vservant_sim\
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+timeout=100000000000\
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+signature={0}/DUT-serv.signature\
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+firmware={0}/{1}.hex'
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def build(self, isa_yaml, platform_yaml):
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ispec = utils.load_yaml(isa_yaml)['hart0']
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self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
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self.isa = 'rv' + self.xlen
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if "I" in ispec["ISA"]:
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self.isa += 'i'
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if "M" in ispec["ISA"]:
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self.isa += 'm'
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if "C" in ispec["ISA"]:
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self.isa += 'c'
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self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
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def runTests(self, testList):
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for testname in testList:
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testentry = testList[testname]
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test = testentry['test_path']
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test_dir = testentry['work_dir']
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file_name = 'serv-{0}'.format(test.rsplit('/',1)[1][:-2])
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elf = '{0}.elf'.format(file_name)
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compile_macros= ' -D' + " -D".join(testentry['macros'])
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marchstr = testentry['isa'].lower()
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compile_run = self.compile_cmd.format(marchstr, test, elf, compile_macros)
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utils.shellCommand(compile_run).run(cwd=test_dir)
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objcopy_run = self.objcopy_cmd.format(elf,file_name)
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utils.shellCommand(objcopy_run).run(cwd=test_dir)
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objdump_run = self.objdump_cmd.format(elf,file_name)
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utils.shellCommand(objdump_run).run(cwd=test_dir)
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hexgen_run = self.hexgen_cmd.format(test_dir,file_name)
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utils.shellCommand(hexgen_run).run()
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sigdump_run = self.sigdump_cmd.format(test_dir,file_name)
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utils.shellCommand(sigdump_run).run()
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if not self.target_run:
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raise SystemExit
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29
verif/plugin-serv/serv_isa.yaml
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29
verif/plugin-serv/serv_isa.yaml
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@@ -0,0 +1,29 @@
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hart_ids: [0]
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hart0:
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ISA: RV32IMCZicsr_Zifencei
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physical_addr_sz: 32
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User_Spec_Version: '2.3'
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supported_xlen: [32]
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misa:
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reset-val: 0x40001104
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rv32:
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accessible: true
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mxl:
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implemented: true
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type:
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warl:
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dependency_fields: []
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legal:
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- mxl[1:0] in [0x1]
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wr_illegal:
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- Unchanged
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extensions:
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implemented: true
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type:
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warl:
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dependency_fields: []
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legal:
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- extensions[25:0] bitmask [0x0001104, 0x0000000]
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wr_illegal:
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- Unchanged
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4
verif/plugin-serv/serv_platform.yaml
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4
verif/plugin-serv/serv_platform.yaml
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@@ -0,0 +1,4 @@
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nmi:
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label: nmi_vector
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reset:
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label: reset_vector
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