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mirror of https://github.com/olofk/serv.git synced 2026-02-01 14:01:55 +00:00

Update Compliance testing framework

This commit is contained in:
Abdulwadoodd
2022-10-03 14:33:11 +05:00
committed by Olof Kindgren
parent 1bdd42acb5
commit 41ae06f6cf
11 changed files with 436 additions and 0 deletions

18
verif/plugin-serv/env/link.ld vendored Normal file
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@@ -0,0 +1,18 @@
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
.text : { *(.text) }
. = ALIGN(0x1000);
.data : { *(.data) }
.data.string : { *(.data.string)}
.bss : { *(.bss) }
_end = .;
}

71
verif/plugin-serv/env/model_test.h vendored Normal file
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#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H
#define RVMODEL_HALT \
la a0, begin_signature; \
la a1, end_signature; \
li a2, 0x80000000; \
complience_halt_loop: \
beq a0, a1, complience_halt_break; \
addi a3, a0, 4; \
complience_halt_loop2: \
addi a3, a3, -1; \
\
lb a4, 0 (a3); \
srai a5, a4, 4; \
andi a5, a5, 0xF; \
li a6, 10; \
blt a5, a6, notLetter; \
addi a5, a5, 39; \
notLetter: \
addi a5, a5, 0x30; \
sw a5, 0 (a2); \
\
srai a5, a4, 0; \
andi a5, a5, 0xF; \
li a6, 10; \
blt a5, a6, notLetter2; \
addi a5, a5, 39; \
notLetter2: \
addi a5, a5, 0x30; \
sw a5, 0 (a2); \
bne a0, a3,complience_halt_loop2; \
addi a0, a0, 4; \
\
li a4, '\n'; \
sw a4, 0 (a2); \
j complience_halt_loop; \
j complience_halt_break; \
complience_halt_break:; \
lui a0,0x90000000>>12; \
sw a3,0(a0);
#define RVMODEL_DATA_BEGIN \
.align 4; .global begin_signature; begin_signature: \
#define RVMODEL_DATA_END \
.align 4; .global end_signature; end_signature: \
#define RVMODEL_BOOT \
.section .text.init; \
.align 4; \
.globl _start; \
_start:
#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
#define RVMODEL_IO_WRITE_STR(_SP, _STR)
#define LOCAL_IO_PUSH(_SP)
#define LOCAL_IO_POP(_SP)
#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
#define RVMODEL_SET_MSW_INT
#define RVMODEL_CLEAR_MSW_INT
#define RVMODEL_CLEAR_MTIMER_INT
#define RVMODEL_CLEAR_MEXT_INT
#endif // _COMPLIANCE_MODEL_H

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import os
import logging
import riscof.utils as utils
from riscof.pluginTemplate import pluginTemplate
logger = logging.getLogger()
class serv(pluginTemplate):
__model__ = "serv"
__version__ = "1.2.0"
def __init__(self, *args, **kwargs):
sclass = super().__init__(*args, **kwargs)
config = kwargs.get('config')
if config is None:
print("Please enter input file paths in configuration.")
raise SystemExit(1)
self.dut_exe = os.path.join(config['PATH'] if 'PATH' in config else "","serv")
self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)
self.pluginpath=os.path.abspath(config['pluginpath'])
self.isa_spec = os.path.abspath(config['ispec'])
self.platform_spec = os.path.abspath(config['pspec'])
if 'target_run' in config and config['target_run']=='0':
self.target_run = False
else:
self.target_run = True
return sclass
def initialise(self, suite, work_dir, archtest_env):
self.work_dir = work_dir
self.suite_dir = suite
self.compile_cmd = 'riscv64-unknown-elf-gcc -march={0} \
-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\
-T '+self.pluginpath+'/env/link.ld\
-I '+self.pluginpath+'/env/\
-I ' + archtest_env + ' {1} -o {2} {3}'
self.objcopy_cmd = 'riscv64-unknown-elf-objcopy -O binary {0} {1}.bin'
self.objdump_cmd = 'riscv64-unknown-elf-objdump -D {0} > {1}.disass'
self.hexgen_cmd = 'python3 makehex.py {0}/{1}.bin > {0}/{1}.hex'
build_serv = 'cd $WORKSPACE \n \
fusesoc library add mdu https://github.com/zeeshanrafique23/mdu\n'
build_serv = build_serv + 'fusesoc run --target=verilator_tb --flag=mdu\
--build --build-root=servant_test servant\
--memsize=8388608 --compressed=1'
utils.shellCommand(build_serv).run()
self.sigdump_cmd = 'cd $WORKSPACE/servant_test/verilator_tb-verilator \n\
./Vservant_sim\
+timeout=100000000000\
+signature={0}/DUT-serv.signature\
+firmware={0}/{1}.hex'
def build(self, isa_yaml, platform_yaml):
ispec = utils.load_yaml(isa_yaml)['hart0']
self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
self.isa = 'rv' + self.xlen
if "I" in ispec["ISA"]:
self.isa += 'i'
if "M" in ispec["ISA"]:
self.isa += 'm'
if "C" in ispec["ISA"]:
self.isa += 'c'
self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
def runTests(self, testList):
for testname in testList:
testentry = testList[testname]
test = testentry['test_path']
test_dir = testentry['work_dir']
file_name = 'serv-{0}'.format(test.rsplit('/',1)[1][:-2])
elf = '{0}.elf'.format(file_name)
compile_macros= ' -D' + " -D".join(testentry['macros'])
marchstr = testentry['isa'].lower()
compile_run = self.compile_cmd.format(marchstr, test, elf, compile_macros)
utils.shellCommand(compile_run).run(cwd=test_dir)
objcopy_run = self.objcopy_cmd.format(elf,file_name)
utils.shellCommand(objcopy_run).run(cwd=test_dir)
objdump_run = self.objdump_cmd.format(elf,file_name)
utils.shellCommand(objdump_run).run(cwd=test_dir)
hexgen_run = self.hexgen_cmd.format(test_dir,file_name)
utils.shellCommand(hexgen_run).run()
sigdump_run = self.sigdump_cmd.format(test_dir,file_name)
utils.shellCommand(sigdump_run).run()
if not self.target_run:
raise SystemExit

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hart_ids: [0]
hart0:
ISA: RV32IMCZicsr_Zifencei
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
misa:
reset-val: 0x40001104
rv32:
accessible: true
mxl:
implemented: true
type:
warl:
dependency_fields: []
legal:
- mxl[1:0] in [0x1]
wr_illegal:
- Unchanged
extensions:
implemented: true
type:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x0001104, 0x0000000]
wr_illegal:
- Unchanged

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nmi:
label: nmi_vector
reset:
label: reset_vector