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boilerplate for external interrupts

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Signed-off-by: Alfred Persson Forsberg <cat@catcream.org>
This commit is contained in:
Alfred Persson Forsberg
2025-01-27 17:09:16 +01:00
committed by Olof Kindgren
parent a72c1e8737
commit 41c0d44e5f
34 changed files with 1337 additions and 44 deletions
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110
bench/decoder_sim.v Normal file
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`default_nettype none
module decoder_sim
(input wire wb_clk,
input wire [31:2] wb_rdt,
input wire wb_en,
output wire ebreak,
output wire jal_or_jalr,
output wire mret,
output wire wfi,
output wire sh_right,
output wire bne_or_bge,
output wire cond_branch,
output wire e_op,
output wire branch_op,
output wire shift_op,
output wire slt_or_branch,
output wire rd_op,
output wire two_stage_op,
output wire dbus_en,
output wire mdu_op,
output wire [2:0] ext_funct3,
output wire bufreg_rs1_en,
output wire bufreg_imm_en,
output wire bufreg_clr_lsb,
output wire bufreg_sh_signed,
output wire ctrl_utype,
output wire ctrl_pc_rel,
output wire alu_sub,
output wire [1:0] alu_bool_op,
output wire alu_cmp_eq,
output wire alu_cmp_sig,
output wire [2:0] alu_rd_sel,
output wire mem_signed,
output wire mem_word,
output wire mem_half,
output wire mem_cmd,
output wire csr_en,
output wire [1:0] csr_addr,
output wire csr_mstatus_en,
output wire csr_mie_en,
output wire csr_mcause_en,
output wire [1:0] csr_source,
output wire csr_d_sel,
output wire csr_imm_en,
output wire mtval_pc,
output wire [3:0] immdec_ctrl,
output wire [3:0] immdec_en,
output wire op_b_source,
output wire rd_mem_en,
output wire rd_csr_en,
output wire rd_alu_en
);
// Instantiate the DUT
serv_decode
#(.PRE_REGISTER (1),
.MDU (0))
dut (
.clk(wb_clk),
.i_wb_rdt(wb_rdt),
.i_wb_en(wb_en),
// Outputs
.o_sh_right(sh_right),
.o_bne_or_bge(bne_or_bge),
.o_cond_branch(cond_branch),
.o_e_op(e_op),
.o_ebreak(ebreak),
.o_wfi(wfi),
.o_branch_op(branch_op),
.o_shift_op(shift_op),
.o_rd_op(rd_op),
.o_two_stage_op(two_stage_op),
.o_dbus_en(dbus_en),
.o_mdu_op(mdu_op),
.o_ext_funct3(ext_funct3),
.o_bufreg_rs1_en(bufreg_rs1_en),
.o_bufreg_imm_en(bufreg_imm_en),
.o_bufreg_clr_lsb(bufreg_clr_lsb),
.o_bufreg_sh_signed(bufreg_sh_signed),
.o_ctrl_jal_or_jalr(jal_or_jalr),
.o_ctrl_utype(ctrl_utype),
.o_ctrl_pc_rel(ctrl_pc_rel),
.o_ctrl_mret(mret),
.o_alu_sub(alu_sub),
.o_alu_bool_op(alu_bool_op),
.o_alu_cmp_eq(alu_cmp_eq),
.o_alu_cmp_sig(alu_cmp_sig),
.o_alu_rd_sel(alu_rd_sel),
.o_mem_signed(mem_signed),
.o_mem_word(mem_word),
.o_mem_half(mem_half),
.o_mem_cmd(mem_cmd),
.o_csr_en(csr_en),
.o_csr_addr(csr_addr),
.o_csr_mstatus_en(csr_mstatus_en),
.o_csr_mie_en(csr_mie_en),
.o_csr_mcause_en(csr_mcause_en),
.o_csr_source(csr_source),
.o_csr_d_sel(csr_d_sel),
.o_csr_imm_en(csr_imm_en),
.o_mtval_pc(mtval_pc),
.o_immdec_ctrl(immdec_ctrl),
.o_immdec_en(immdec_en),
.o_op_b_source(op_b_source),
.o_rd_mem_en(rd_mem_en),
.o_rd_csr_en(rd_csr_en),
.o_rd_alu_en(rd_alu_en)
);
endmodule

157
bench/decoder_tb.cpp Normal file
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#include <fcntl.h>
#include <cstdint>
#include <csignal>
#include <iostream>
#include <fstream>
#include <memory>
#include <ctime>
#include <string>
#include "verilated_vcd_c.h"
#include "Vdecoder_sim.h"
void INThandler(int signal) {
std::cout << "\nCaught ctrl-c\n";
std::exit(0);
}
void test_instruction(Vdecoder_sim *top, const std::string& instr_name, uint32_t instr);
void cycle(Vdecoder_sim *top);
int main(int argc, char** argv, char** env) {
Verilated::commandArgs(argc, argv);
Vdecoder_sim *top = new Vdecoder_sim;
std::signal(SIGINT, INThandler);
top->wb_clk = 0;
top->wb_rdt = 0;
top->wb_en = 0;
std::cout << "Testing decoder\n";
test_instruction(top, "jalr", 0x0000006F);
test_instruction(top, "mret", 0x30200073);
test_instruction(top, "ebreak", 0x00100073);
test_instruction(top, "wfi", 0x10500073);
test_instruction(top, "add", 0x00000033);
test_instruction(top, "addi", 0x00000013);
test_instruction(top, "sub", 0x40000033);
test_instruction(top, "and", 0x00007033);
test_instruction(top, "andi", 0x00007013);
test_instruction(top, "or", 0x00006033);
test_instruction(top, "ori", 0x00006013);
test_instruction(top, "xor", 0x00004033);
test_instruction(top, "xori", 0x00004013);
test_instruction(top, "sll", 0x00001033);
test_instruction(top, "slli", 0x00001013);
test_instruction(top, "srl", 0x00005033);
test_instruction(top, "srli", 0x00005013);
test_instruction(top, "sra", 0x40005033);
test_instruction(top, "srai", 0x40005013);
test_instruction(top, "lui", 0x00000037);
test_instruction(top, "auipc", 0x00000017);
test_instruction(top, "lw", 0x00002003);
test_instruction(top, "lh", 0x00001003);
test_instruction(top, "lhu", 0x00005003);
test_instruction(top, "lb", 0x00000003);
test_instruction(top, "lbu", 0x00004003);
test_instruction(top, "sw", 0x00002023);
test_instruction(top, "sh", 0x00001023);
test_instruction(top, "sb", 0x00000023);
test_instruction(top, "jal", 0x0000006F);
test_instruction(top, "jalr", 0x00000067);
test_instruction(top, "beq", 0x00000063);
test_instruction(top, "bne", 0x00001063);
test_instruction(top, "blt", 0x00004063);
test_instruction(top, "bge", 0x00005063);
test_instruction(top, "bltu", 0x00006063);
test_instruction(top, "bgeu", 0x00007063);
test_instruction(top, "slt", 0x00002033);
test_instruction(top, "slti", 0x00002013);
test_instruction(top, "sltu", 0x00003033);
test_instruction(top, "sltiu", 0x00003013);
test_instruction(top, "ecall", 0x00000073);
test_instruction(top, "ebreak", 0x00100073);
test_instruction(top, "fence", 0x0000000F);
test_instruction(top, "fence.i", 0x0000100F);
test_instruction(top, "csrrw", 0x00001073);
test_instruction(top, "csrrs", 0x00002073);
test_instruction(top, "csrrc", 0x00003073);
test_instruction(top, "csrrwi", 0x00005073);
test_instruction(top, "csrrsi", 0x00006073);
test_instruction(top, "csrrci", 0x00007073);
return 0;
}
void cycle(Vdecoder_sim *top) {
top->eval();
top->wb_clk = 0;
top->eval();
top->wb_clk = 1;
top->eval();
}
void test_instruction(Vdecoder_sim *top, const std::string& instr_name, uint32_t instr) {
std::ofstream outfile(instr_name + ".txt");
std::cout << "Testing " << instr_name << "\n";
outfile << "Testing " << instr_name << "\n";
top->wb_rdt = instr >> 2;
top->wb_en = 1;
cycle(top);
outfile << "jal_or_jalr: " << std::to_string(top->jal_or_jalr) << std::endl;
outfile << "ebreak: " << std::to_string(top->ebreak) << std::endl;
outfile << "mret: " << std::to_string(top->mret) << std::endl;
outfile << "wfi: " << std::to_string(top->wfi) << std::endl;
outfile << "sh_right: " << std::to_string(top->sh_right) << std::endl;
outfile << "bne_or_bge: " << std::to_string(top->bne_or_bge) << std::endl;
outfile << "cond_branch: " << std::to_string(top->cond_branch) << std::endl;
outfile << "e_op: " << std::to_string(top->e_op) << std::endl;
outfile << "branch_op: " << std::to_string(top->branch_op) << std::endl;
outfile << "shift_op: " << std::to_string(top->shift_op) << std::endl;
outfile << "slt_or_branch: " << std::to_string(top->slt_or_branch) << std::endl;
outfile << "rd_op: " << std::to_string(top->rd_op) << std::endl;
outfile << "two_stage_op: " << std::to_string(top->two_stage_op) << std::endl;
outfile << "dbus_en: " << std::to_string(top->dbus_en) << std::endl;
outfile << "mdu_op: " << std::to_string(top->mdu_op) << std::endl;
outfile << "ext_funct3: " << std::to_string(top->ext_funct3) << std::endl;
outfile << "bufreg_rs1_en: " << std::to_string(top->bufreg_rs1_en) << std::endl;
outfile << "bufreg_imm_en: " << std::to_string(top->bufreg_imm_en) << std::endl;
outfile << "bufreg_clr_lsb: " << std::to_string(top->bufreg_clr_lsb) << std::endl;
outfile << "bufreg_sh_signed: " << std::to_string(top->bufreg_sh_signed) << std::endl;
outfile << "ctrl_utype: " << std::to_string(top->ctrl_utype) << std::endl;
outfile << "ctrl_pc_rel: " << std::to_string(top->ctrl_pc_rel) << std::endl;
outfile << "alu_sub: " << std::to_string(top->alu_sub) << std::endl;
outfile << "alu_bool_op: " << std::to_string(top->alu_bool_op) << std::endl;
outfile << "alu_cmp_eq: " << std::to_string(top->alu_cmp_eq) << std::endl;
outfile << "alu_cmp_sig: " << std::to_string(top->alu_cmp_sig) << std::endl;
outfile << "alu_rd_sel: " << std::to_string(top->alu_rd_sel) << std::endl;
outfile << "mem_signed: " << std::to_string(top->mem_signed) << std::endl;
outfile << "mem_word: " << std::to_string(top->mem_word) << std::endl;
outfile << "mem_half: " << std::to_string(top->mem_half) << std::endl;
outfile << "mem_cmd: " << std::to_string(top->mem_cmd) << std::endl;
outfile << "csr_en: " << std::to_string(top->csr_en) << std::endl;
outfile << "csr_addr: " << std::to_string(top->csr_addr) << std::endl;
outfile << "csr_mstatus_en: " << std::to_string(top->csr_mstatus_en) << std::endl;
outfile << "csr_mie_en: " << std::to_string(top->csr_mie_en) << std::endl;
outfile << "csr_mcause_en: " << std::to_string(top->csr_mcause_en) << std::endl;
outfile << "csr_source: " << std::to_string(top->csr_source) << std::endl;
outfile << "csr_d_sel: " << std::to_string(top->csr_d_sel) << std::endl;
outfile << "csr_imm_en: " << std::to_string(top->csr_imm_en) << std::endl;
outfile << "mtval_pc: " << std::to_string(top->mtval_pc) << std::endl;
outfile << "immdec_ctrl: " << std::to_string(top->immdec_ctrl) << std::endl;
outfile << "immdec_en: " << std::to_string(top->immdec_en) << std::endl;
outfile << "op_b_source: " << std::to_string(top->op_b_source) << std::endl;
outfile << "rd_mem_en: " << std::to_string(top->rd_mem_en) << std::endl;
outfile << "rd_csr_en: " << std::to_string(top->rd_csr_en) << std::endl;
outfile << "rd_alu_en: " << std::to_string(top->rd_alu_en) << std::endl;
assert(!(top->wfi && instr_name != "wfi"));
top->wb_en = 0;
cycle(top);
outfile.close();
}

42
bench/servant_external_sim.v Normal file
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`default_nettype none
module servant_external_sim
(input wire wb_clk,
input wire wb_rst,
input wire ext_irq,
output wire [31:0] pc_adr,
output wire pc_vld,
output wire q,
output wire mret
);
parameter memfile = "";
parameter memsize = 8192;
parameter width = 1;
parameter with_csr = 1;
parameter compressed = 0;
parameter align = compressed;
parameter interrupt_time = 3000;
reg [1023:0] firmware_file;
initial
if ($value$plusargs("firmware=%s", firmware_file)) begin
$display("Loading RAM from %0s", firmware_file);
$readmemh(firmware_file, dut.servant.ram.mem);
end
servant_sleep_dummy
#(.memfile (memfile),
.memsize (memsize),
.width (width),
.debug (1'b1),
.sim (1),
.with_csr (with_csr),
.compress (compressed[0:0]),
.align (align[0:0]))
dut(wb_clk, wb_rst, ext_irq, q);
assign pc_adr = dut.servant.wb_mem_adr;
assign pc_vld = dut.servant.wb_mem_ack;
assign mret = dut.servant.cpu.cpu.mret;
endmodule

126
bench/servant_external_tb.cpp Normal file
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#include <fcntl.h>
#include <stdint.h>
#include <signal.h>
#include "verilated_vcd_c.h"
#include "Vservant_external_sim.h"
#include <ctime>
using namespace std;
static bool done;
vluint64_t main_time = 0; // Current simulation time
// This is a 64-bit integer to reduce wrap over issues and
// allow modulus. You can also use a double, if you wish.
double sc_time_stamp () { // Called by $time in Verilog
return main_time; // converts to double, to match
// what SystemC does
}
void INThandler(int signal) {
printf("\nCaught ctrl-c\n");
done = true;
}
int reset(Vservant_external_sim *, VerilatedVcdC *);
int timer_test(Vservant_external_sim *, VerilatedVcdC *,
vluint64_t, vluint64_t);
int main(int argc, char **argv, char **env) {
Verilated::commandArgs(argc, argv);
Vservant_external_sim* top = new Vservant_external_sim;
VerilatedVcdC * tfp = 0;
const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
if (vcd[0]) {
Verilated::traceEverOn(true);
tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("trace.vcd");
}
signal(SIGINT, INThandler);
vluint64_t timeout = 0;
const char *arg_timeout = Verilated::commandArgsPlusMatch("timeout=");
if (arg_timeout[0])
timeout = atoi(arg_timeout+9);
vluint64_t interrupt_time = 1500;
const char *arg_interrupt_time =
Verilated::commandArgsPlusMatch("interrupt_time=");
if (arg_interrupt_time[0]) {
interrupt_time = atoi(arg_interrupt_time);
}
vluint64_t vcd_start = 0;
const char *arg_vcd_start = Verilated::commandArgsPlusMatch("vcd_start=");
if (arg_vcd_start[0])
vcd_start = atoi(arg_vcd_start+11);
int cur_cycle = 0;
int last_cycle = 0;
std::time_t last_time = std::time(nullptr);
top->wb_clk = 1;
top->ext_irq = 0;
bool q = top->q;
int clock = 0;
reset(top, tfp);
timer_test(top, tfp, timeout, interrupt_time);
if (tfp) {
tfp->close();
}
exit(0);
}
int reset(Vservant_external_sim *top, VerilatedVcdC *tfp) {
top->wb_rst = 1;
for (int i = 0; i < 10; i++) {
top->wb_clk = !top->wb_clk;
top->eval();
}
top->wb_clk = !top->wb_clk;
top->wb_rst = 0;
return 0;
}
int timer_test(Vservant_external_sim *top, VerilatedVcdC *tfp,
vluint64_t timeout, vluint64_t interrupt_time) {
int clock = 0;
while (Verilated::gotFinish()) {
top->eval();
if (top->wb_clk) {
clock++;
}
if (tfp && top->wb_clk) {
tfp->dump(clock);
}
if (clock >= interrupt_time && clock <= interrupt_time + 100) {
if (top->ext_irq == 0) {
printf("interrupting %d\n", clock);
}
top->ext_irq = 1;
} else {
top->ext_irq = 0;
}
if (top->wb_clk && top->pc_vld && top->pc_adr) {
std::this_thread::sleep_for(std::chrono::milliseconds(500));
printf("%d | %d\n", clock, top->pc_adr);
if (top->mret) {
printf("mret detected, exiting\n");
exit(0);
}
}
if (timeout && (clock >= timeout)) {
printf("Timeout: Exiting at time %d\n", clock);
exit(0);
}
top->wb_clk = !top->wb_clk;
}
}

2
bench/servant_sim.v
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@@ -29,7 +29,7 @@ module servant_sim
.with_csr (with_csr),
.compress (compressed[0:0]),
.align (align[0:0]))
dut(wb_clk, wb_rst, q);
dut(wb_clk, wb_clk, wb_rst, q);
assign pc_adr = dut.wb_mem_adr;
assign pc_vld = dut.wb_mem_ack;

43
bench/servant_timer_sim.v Normal file
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@@ -0,0 +1,43 @@
`default_nettype none
module servant_timer_sim
(input wire wb_clk,
input wire wb_rst,
input wire timer_clk,
output wire [31:0] pc_adr,
output wire pc_vld,
output wire q,
output wire timer_irq
);
parameter memfile = "";
parameter memsize = 8192;
parameter width = 1;
parameter with_csr = 1;
parameter compressed = 0;
parameter align = compressed;
wire sleep;
wire ext_irq;
reg [1023:0] firmware_file;
initial
if ($value$plusargs("firmware=%s", firmware_file)) begin
$display("Loading RAM from %0s", firmware_file);
$readmemh(firmware_file, dut.servant.ram.mem);
end
servant_sleep_dummy
#(.memfile (memfile),
.memsize (memsize),
.width (width),
.debug (1'b1),
.sim (1),
.with_csr (with_csr),
.compress (compressed[0:0]),
.align (align[0:0]))
dut(wb_clk, wb_rst, ext_irq, q);
assign pc_adr = dut.servant.wb_mem_adr;
assign pc_vld = dut.servant.wb_mem_ack;
assign timer_irq = dut.servant.timer_irq;
endmodule

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bench/servant_timer_tb.cpp Normal file
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#include <fcntl.h>
#include <stdint.h>
#include <signal.h>
#include "verilated_vcd_c.h"
#include "Vservant_timer_sim.h"
#include <ctime>
using namespace std;
static bool done;
vluint64_t main_time = 0; // Current simulation time
// This is a 64-bit integer to reduce wrap over issues and
// allow modulus. You can also use a double, if you wish.
double sc_time_stamp () { // Called by $time in Verilog
return main_time; // converts to double, to match
// what SystemC does
}
void INThandler(int signal)
{
printf("\nCaught ctrl-c\n");
done = true;
}
int main(int argc, char **argv, char **env)
{
int baud_rate = 0;
Verilated::commandArgs(argc, argv);
Vservant_timer_sim* top = new Vservant_timer_sim;
VerilatedVcdC * tfp = 0;
const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
if (vcd[0]) {
Verilated::traceEverOn(true);
tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("trace.vcd");
}
signal(SIGINT, INThandler);
vluint64_t timeout = 0;
const char *arg_timeout = Verilated::commandArgsPlusMatch("timeout=");
if (arg_timeout[0])
timeout = atoi(arg_timeout+9);
vluint64_t vcd_start = 0;
const char *arg_vcd_start = Verilated::commandArgsPlusMatch("vcd_start=");
if (arg_vcd_start[0])
vcd_start = atoi(arg_vcd_start+11);
int cur_cycle = 0;
int last_cycle = 0;
std::time_t last_time = std::time(nullptr);
top->wb_clk = 0;
top->timer_clk = 0;
bool q = top->q;
int clock = 0;
top->eval();
while (!(done || Verilated::gotFinish())) {
top->eval();
if (top->wb_clk) {
clock++;
}
top->wb_rst = main_time < 1000;
if (tfp) {
tfp->dump(main_time);
}
if (top->wb_clk && top->pc_vld && top->pc_adr) {
std::this_thread::sleep_for(std::chrono::milliseconds(500));
printf("%d | %d\n", clock, top->pc_adr);
}
if (timeout && (main_time >= timeout)) {
printf("Timeout: Exiting at time %lu\n", main_time);
done = true;
}
top->wb_clk = !top->wb_clk;
top->timer_clk = top->wb_clk;
main_time+=31.25;
}
if (tfp) {
tfp->close();
}
exit(0);
}