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boilerplate for external interrupts

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Signed-off-by: Alfred Persson Forsberg <cat@catcream.org>
This commit is contained in:
Alfred Persson Forsberg
2025-01-27 17:09:16 +01:00
committed by Olof Kindgren
parent a72c1e8737
commit 41c0d44e5f
34 changed files with 1337 additions and 44 deletions
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17
data/nexys_4.xdc Normal file
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## 100 MHz Clock Signal (period 10)
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { i_clk }];
create_clock -add -name sys_clk_pin -period 10 -waveform {0 5} [get_ports { i_clk }];
## External interrupt (to BTNL)
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports {ext_irq}];
## LEDs
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS33 } [get_ports { q }];
## UART
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { o_uart_tx }];
set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { i_rst }]; # ACTIVE LOW !!!
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

25
data/nexys_a7.xdc
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports i_clk];
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports q]
## 100 MHz Clock Signal (period 10)
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { i_clk }];
create_clock -add -name sys_clk_pin -period 10 -waveform {0 5} [get_ports { i_clk }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];
## External interrupt (to BTNL)
set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {ext_irq}];
## LEDs (LED0)
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { q }];
## UART
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { o_uart_tx }];
set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { i_rst }]; # ACTIVE LOW !!!
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
## DEBUG (JA1)
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { debug_wb_clk }]; #JA1
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { q }]; #JA2
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { debug_sleep_req }]; #JA3
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { debug_wakeup_req }]; #JA4