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boilerplate for external interrupts

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Signed-off-by: Alfred Persson Forsberg <cat@catcream.org>
This commit is contained in:
Alfred Persson Forsberg
2025-01-27 17:09:16 +01:00
committed by Olof Kindgren
parent a72c1e8737
commit 41c0d44e5f
34 changed files with 1337 additions and 44 deletions
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30
servant/servant.v
View File

@@ -2,8 +2,11 @@
module servant
(
input wire wb_clk,
input wire main_clk,
input wire wb_rst,
output wire q);
input wire ext_irq,
output wire q,
output reg o_sleep);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
@@ -22,6 +25,12 @@ module servant
localparam [0:0] with_mdu = 1'b0;
`endif
`ifdef EI
localparam [0:0] with_ei = 1'b1;
`else
localparam [0:0] with_ei = 1'b0;
`endif
localparam aw = $clog2(memsize);
localparam csr_regs = with_csr*4;
@@ -63,6 +72,8 @@ module servant
wire [rf_l2d-1:0] rf_raddr;
wire rf_ren;
wire [rf_width-1:0] rf_rdata;
wire sleep_req;
wire wakeup_req;
servant_mux servant_mux
(
@@ -106,7 +117,7 @@ module servant
#(.RESET_STRATEGY (reset_strategy),
.WIDTH (32))
timer
(.i_clk (wb_clk),
(.i_clk (main_clk),
.i_rst (wb_rst),
.o_irq (timer_irq),
.i_wb_cyc (wb_timer_stb),
@@ -140,12 +151,16 @@ module servant
.debug (debug),
.with_c (compress[0]),
.with_csr (with_csr[0]),
.with_mdu (with_mdu))
.with_mdu (with_mdu),
.with_ei (with_ei))
cpu
(
.i_clk (wb_clk),
.i_rst (wb_rst),
.i_timer_irq (timer_irq),
.i_external_irq (ext_irq),
.o_wakeup_req (wakeup_req),
.o_sleep_req (sleep_req),
.o_wb_mem_adr (wb_mem_adr),
.o_wb_mem_dat (wb_mem_dat),
@@ -170,4 +185,13 @@ module servant
.o_rf_ren (rf_ren),
.i_rf_rdata (rf_rdata));
always @(posedge main_clk) begin
if (sleep_req)
o_sleep <= 1;
if (wakeup_req)
o_sleep <= 0;
if (wb_rst)
o_sleep <= 0;
end
endmodule

53
servant/servant_nexys_4.v Normal file
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@@ -0,0 +1,53 @@
`default_nettype none
module servant_nexys_4
(
input wire i_clk,
input wire i_rst,
input wire ext_irq,
output wire o_uart_tx,
output wire q);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire main_clk;
wire wb_clk;
wire wb_rst;
wire sleep_req;
wire wakeup_req;
reg sleep;
always @(posedge main_clk) begin
if (sleep_req)
sleep <= 0;
if (wakeup_req)
sleep <= 1;
if (wb_rst)
sleep <= 1;
end
assign o_uart_tx = q;
servant_nexys_4_clock_gen
clock_gen
(.i_clk (i_clk),
.i_rst (i_rst),
.i_clk0_en (sleep),
.i_clk1_en (1),
.o_clk0 (main_clk),
.o_clk1 (wb_clk),
.o_rst (wb_rst));
servant
#(.memfile (memfile),
.memsize (memsize))
servant
(.wb_clk (wb_clk),
.wb_rst (wb_rst),
.q (q),
.o_sleep_req (sleep_req),
.o_wakeup_req (wakeup_req));
endmodule
`default_nettype wire

54
servant/servant_nexys_4_clock_gen.v Normal file
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@@ -0,0 +1,54 @@
`default_nettype none
module servant_nexys_4_clock_gen
(input wire i_clk,
input wire i_rst,
input wire i_clk0_en,
input wire i_clk1_en,
output wire o_clk0,
output wire o_clk1,
output reg o_rst);
wire clkfb;
wire locked;
wire pll_rst;
wire pll_clk;
reg locked_r;
assign pll_rst = !i_rst;
MMCME2_BASE
#(.CLKIN1_PERIOD (10), //100MHz
/* Set VCO frequency to 100*8.0=800 MHz
Allowed values are 2.0 to 64.0. Resulting VCO freq
needs to be 600-1200MHz */
.CLKFBOUT_MULT_F (8.000),
.CLKOUT0_DIVIDE_F (25.000)) // 800/25 = 32 MHz
pll
(.CLKIN1 (i_clk),
.RST (pll_rst),
.CLKOUT0 (pll_clk),
.LOCKED (locked),
.CLKFBOUT (clkfb),
.CLKFBIN (clkfb));
always @(posedge pll_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
BUFGCE clk0_buf
(
.I (pll_clk),
.O (o_clk0),
.CE (i_clk0_en));
BUFGCE clk1_buf
(
.I (pll_clk),
.O (o_clk1),
.CE (i_clk0_en));
endmodule
`default_nettype wire

42
servant/servant_nexys_a7.v Normal file
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@@ -0,0 +1,42 @@
`default_nettype none
module servant_nexys_a7
(
input wire i_clk,
input wire i_rst,
input wire ext_irq,
output wire o_uart_tx,
output wire q);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire main_clk;
wire wb_clk;
wire wb_rst;
wire sleep;
assign o_uart_tx = q;
servant_nexys_a7_clock_gen
clock_gen
(.i_clk (i_clk),
.i_rst (i_rst),
.i_clk0_en (1),
.i_clk1_en (!sleep),
.o_clk0 (main_clk),
.o_clk1 (wb_clk),
.o_rst (wb_rst));
servant
#(.memfile (memfile),
.memsize (memsize))
servant
(.wb_clk (wb_clk),
.main_clk (main_clk),
.wb_rst (wb_rst),
.q (q),
.ext_irq (ext_irq),
.o_sleep (sleep));
endmodule
`default_nettype wire

57
servant/servant_nexys_a7_clock_gen.v Normal file
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@@ -0,0 +1,57 @@
`default_nettype none
module servant_nexys_a7_clock_gen
(input wire i_clk,
input wire i_rst,
input wire i_clk0_en,
input wire i_clk1_en,
output wire o_clk0,
output wire o_clk1,
output reg o_rst);
wire clkfb;
wire locked;
wire pll_rst;
wire pll_clk;
reg locked_r;
assign pll_rst = !i_rst;
MMCME2_BASE
#(.CLKIN1_PERIOD (10), //100MHz
/* Set VCO frequency to 100*8.0=800 MHz
Allowed values are 2.0 to 64.0. Resulting VCO freq
needs to be 600-1200MHz */
.CLKFBOUT_MULT_F (6.000),
.CLKOUT0_DIVIDE_F (64.000)) // 800/25 = 32 MHz
pll
(.CLKIN1 (i_clk),
.RST (pll_rst),
.CLKOUT0 (pll_clk),
.LOCKED (locked),
.CLKFBOUT (clkfb),
.CLKFBIN (clkfb));
always @(posedge pll_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
BUFGCE clk0_buf
(
.I (pll_clk),
.O (o_clk0),
.CE (i_clk0_en));
BUFGCE clk1_buf
(
.I (pll_clk),
.O (o_clk1),
.CE (i_clk1_en));
endmodule
`default_nettype wire

47
servant/servant_sleep_dummy.v Normal file
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@@ -0,0 +1,47 @@
`default_nettype none
module servant_sleep_dummy
(
input wire i_clk,
input wire i_rst,
input wire ext_irq,
output wire q);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter reset_strategy = "MINI";
parameter width = 1;
parameter sim = 0;
parameter [0:0] debug = 1'b0;
parameter with_csr = 1;
parameter [0:0] compress = 0;
parameter [0:0] align = compress;
wire sleep;
wire wb_clk;
wire sleep_req;
wire wakeup_req;
assign wb_clk = i_clk & !sleep;
servant #(
.memfile(memfile),
.memsize(memsize),
.reset_strategy(reset_strategy),
.width(width),
.sim(sim),
.debug(debug),
.with_csr(with_csr),
.compress(compress),
.align(align)
)
servant (
.wb_clk (wb_clk),
.main_clk (i_clk),
.wb_rst (i_rst),
.ext_irq (ext_irq),
.q (q),
.o_sleep (sleep));
endmodule
`default_nettype wire