From 468e99ac7c61b2725a6561c0e29ca9c6dc0e8299 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 7 Dec 2018 22:55:55 +0100 Subject: [PATCH] Syntax fixes to please Quartus --- rtl/serv_csr.v | 2 +- rtl/shift_reg.v | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/rtl/serv_csr.v b/rtl/serv_csr.v index 3b4a6ef..9db26bb 100644 --- a/rtl/serv_csr.v +++ b/rtl/serv_csr.v @@ -66,7 +66,7 @@ module serv_csr assign o_q = csr_out; - wire o_timer_irq_en = mstatus_mie & mie_mtie; + assign o_timer_irq_en = mstatus_mie & mie_mtie; always @(posedge i_clk) begin if (i_en & (i_cnt == 3) & (i_csr_sel == CSR_SEL_MSTATUS)) diff --git a/rtl/shift_reg.v b/rtl/shift_reg.v index 3a4e51b..0b3d504 100644 --- a/rtl/shift_reg.v +++ b/rtl/shift_reg.v @@ -1,5 +1,6 @@ module shift_reg - #(parameter LEN = 0) + #(parameter LEN = 0, + parameter INIT = 0) ( input wire clk, input wire i_en, @@ -7,8 +8,6 @@ module shift_reg output wire o_q, output wire [LEN-2:0] o_par); - parameter INIT = 0; - reg [LEN-1:0] data = INIT; assign o_q = data[0]; assign o_par = data[LEN-1:1];