diff --git a/riscv-target/serv/compliance_io.h b/riscv-target/serv/compliance_io.h
new file mode 100644
index 0000000..65e0148
--- /dev/null
+++ b/riscv-target/serv/compliance_io.h
@@ -0,0 +1,36 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _COMPLIANCE_IO_H
+#define _COMPLIANCE_IO_H
+
+//-----------------------------------------------------------------------
+// RV IO Macros (Non functional)
+//-----------------------------------------------------------------------
+
+#define RVTEST_IO_INIT
+#define RVTEST_IO_WRITE_STR(_STR)
+#define RVTEST_IO_CHECK()
+#define RVTEST_IO_ASSERT_GPR_EQ(_R, _I)
+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#endif // _COMPLIANCE_IO_H
diff --git a/riscv-target/serv/compliance_test.h b/riscv-target/serv/compliance_test.h
new file mode 100644
index 0000000..43d37bb
--- /dev/null
+++ b/riscv-target/serv/compliance_test.h
@@ -0,0 +1,67 @@
+// RISC-V Compliance Test Header File
+// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
+// See LICENSE for license details.
+//
+// Description: Common header file for RV32I tests
+
+#ifndef _COMPLIANCE_TEST_H
+#define _COMPLIANCE_TEST_H
+
+//-----------------------------------------------------------------------
+// RV Compliance Macros
+//-----------------------------------------------------------------------
+
+#define RV_COMPLIANCE_HALT              \
+la a0, data_begin;	 \
+        la a1, data_end; \
+        li a2, 0x10000000; \
+complience_halt_loop: \
+        beq a0, a1, complience_halt_break; \
+        addi a3, a0, 16; \
+complience_halt_loop2: \
+        addi a3, a3, -1; \
+	\
+        lb a4, 0 (a3); \
+        srai a5, a4, 4; \
+        andi a5, a5, 0xF; \
+        li a6, 10; \
+        blt a5, a6, notLetter; \
+        addi a5, a5, 39; \
+notLetter: \
+        addi a5, a5, 0x30; \
+        sw a5, 0 (a2); \
+	\
+        srai a5, a4, 0; \
+        andi a5, a5, 0xF; \
+        li a6, 10; \
+        blt a5, a6, notLetter2; \
+        addi a5, a5, 39; \
+notLetter2: \
+        addi a5, a5, 0x30; \
+        sw a5, 0 (a2); \
+        bne a0, a3,complience_halt_loop2;  \
+        addi a0, a0, 16; \
+	\
+        li a4, '\n'; \
+        sw a4, 0 (a2); \
+        j complience_halt_loop; \
+  j complience_halt_break;		\
+complience_halt_break:; \
+	lui	a0,0x20000000>>12;	\
+	sw	a3,0(a0);		
+
+#define RV_COMPLIANCE_RV32M
+
+#define RV_COMPLIANCE_CODE_BEGIN                                              \
+        .section .text.init;                                            \
+        .align  4;                                                      \
+        .globl _start;                                                  \
+_start:                                                                 \
+
+#define RV_COMPLIANCE_CODE_END
+
+#define RV_COMPLIANCE_DATA_BEGIN .align 4; .global data_begin; data_begin:
+
+#define RV_COMPLIANCE_DATA_END .align 4; .global data_end; data_end:
+
+#endif
diff --git a/riscv-target/serv/device/rv32i/Makefile.include b/riscv-target/serv/device/rv32i/Makefile.include
new file mode 100644
index 0000000..5f8d4d0
--- /dev/null
+++ b/riscv-target/serv/device/rv32i/Makefile.include
@@ -0,0 +1,25 @@
+TARGET_SIM ?= server
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_TARGET=\
+    $(TARGET_SIM) \
+        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +firmware=$(work_dir_isa)$<.hex 2> $(work_dir_isa)/$@
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
+		-I$(ROOTDIR)/riscv-test-env/ \
+		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+		-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \
+		-o $(work_dir_isa)/$$@; \
+	$$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@  $(work_dir_isa)/$$@.bin; \
+	$$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \
+	python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $(work_dir_isa)/$$@.bin 2048 > $(work_dir_isa)/$$@.hex;
diff --git a/riscv-target/serv/link.ld b/riscv-target/serv/link.ld
new file mode 100644
index 0000000..db7be33
--- /dev/null
+++ b/riscv-target/serv/link.ld
@@ -0,0 +1,18 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0x00000000;
+  .text.init : { *(.text.init) }
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+  . = ALIGN(0x1000);
+  .data : { *(.data) }
+  .data.string : { *(.data.string)}
+  .bss : { *(.bss) }
+  _end = .;
+}
+
diff --git a/riscv-target/serv/makehex.py b/riscv-target/serv/makehex.py
new file mode 100644
index 0000000..419b378
--- /dev/null
+++ b/riscv-target/serv/makehex.py
@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+#
+# This is free and unencumbered software released into the public domain.
+#
+# Anyone is free to copy, modify, publish, use, compile, sell, or
+# distribute this software, either in source code form or as a compiled
+# binary, for any purpose, commercial or non-commercial, and by any
+# means.
+
+from sys import argv
+
+binfile = argv[1]
+nwords = int(argv[2])
+
+with open(binfile, "rb") as f:
+    bindata = f.read()
+
+assert len(bindata) < 4*nwords
+assert len(bindata) % 4 == 0
+
+for i in range(nwords):
+    if i < len(bindata) // 4:
+        w = bindata[4*i : 4*i+4]
+        print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0]))
+    else:
+        print("0")
+