remove redundant ALU control signal

rtl/serv_alu.v

@@ -11,7 +11,7 @@ module serv_alu
    input wire [1:0] i_bool_op,
    input wire 	    i_cmp_eq,
    input wire 	    i_cmp_sig,
-   input wire [3:0] i_rd_sel,
+   input wire [2:0] i_rd_sel,
    //Data
    input wire 	    i_rs1,
    input wire 	    i_op_b,
@@ -42,10 +42,10 @@ module serv_alu
    localparam [15:0] BOOL_LUT = 16'h8E06;//And, Or, 0, xor
    wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, i_op_b}];
 
-   assign o_rd = (i_rd_sel[0] & result_add) |
+   assign o_rd = i_buf |
-                 (i_rd_sel[1] & i_buf) |
+                 (i_rd_sel[0] & result_add) |
-                 (i_rd_sel[2] & cmp_r & i_cnt0) |
+                 (i_rd_sel[1] & cmp_r & i_cnt0) |
-                 (i_rd_sel[3] & result_bool);
+                 (i_rd_sel[2] & result_bool);
 
    always @(posedge clk) begin
       add_cy_r <= i_en ? add_cy : i_sub;

rtl/serv_decode.v

@@ -31,7 +31,7 @@ module serv_decode
    output wire [1:0] o_alu_bool_op,
    output wire 	     o_alu_cmp_eq,
    output wire 	     o_alu_cmp_sig,
-   output wire [3:0] o_alu_rd_sel,
+   output wire [2:0] o_alu_rd_sel,
    //To mem IF
    output wire 	     o_mem_signed,
    output wire 	     o_mem_word,
@@ -205,9 +205,8 @@ module serv_decode
    assign o_immdec_ctrl[3] = opcode[4];
 
    assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub
-   assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift
+   assign o_alu_rd_sel[1] = (funct3[2:1] == 2'b01); //SLT*
-   assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT*
+   assign o_alu_rd_sel[2] = funct3[2]; //Bool
-   assign o_alu_rd_sel[3] = funct3[2]; //Bool
    always @(posedge clk) begin
       if (i_wb_en) begin
          funct3        <= i_wb_rdt[14:12];

rtl/serv_top.v

@@ -115,7 +115,7 @@ module serv_top
    wire          alu_cmp_eq;
    wire          alu_cmp_sig;
    wire          alu_cmp;
-   wire [3:0]    alu_rd_sel;
+   wire [2:0]    alu_rd_sel;
 
    wire          rs1;
    wire          rs2;