From 61c8a6b8867cde7546821a5e03edb93992bf5475 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Sun, 10 Nov 2019 17:39:17 +0100
Subject: [PATCH] add arty_a7_35t support

---
 README.md            | 10 +++++++++-
 data/arty_a7_35t.xdc | 10 ++++++++++
 servant.core         | 13 +++++++++++++
 3 files changed, 32 insertions(+), 1 deletion(-)
 create mode 100644 data/arty_a7_35t.xdc

diff --git a/README.md b/README.md
index 94bc759..fdcc38e 100644
--- a/README.md
+++ b/README.md
@@ -70,7 +70,7 @@ Run the compliance tests
 
 ## Run on hardware
 
-Only supported so far is a single threaded Zephyr hello world example on the icebreaker and tinyFPGA BX boards. Some 
+Only supported so far is a single threaded Zephyr hello world example on the icebreaker tinyFPGA BX and arty A7 35T boards. Some
 packages should be installed before running it (and shoud be accessible in your PATH variable):
 - [icestorm](https://github.com/cliffordwolf/icestorm).
 - [nextpnr](https://github.com/YosysHQ/nextpnr).
@@ -102,6 +102,14 @@ Pin 9 is used for UART output with 57600 baud rate.
     cd $SERV/workspace
     fusesoc run --target=icebreaker servant
 
+### Arty A7 35T
+
+Pin D10 (uart_rxd_out) is used for UART output with 57600 baud rate (to use
+blinky.hex change D10 to H5 (led[4]) in data/arty_a7_35t.xdc).
+
+    cd $SERV/workspace
+    fusesoc run --target=arty_a7_35t servant
+
 ## Other targets
 
 The above targets are run on the servant SoC, but there are some targets defined for the CPU itself. Verilator can be run in lint mode to check for design problems by running
diff --git a/data/arty_a7_35t.xdc b/data/arty_a7_35t.xdc
new file mode 100644
index 0000000..e6fcbfa
--- /dev/null
+++ b/data/arty_a7_35t.xdc
@@ -0,0 +1,10 @@
+set_property -dict {PACKAGE_PIN E3  IOSTANDARD LVCMOS33 } [get_ports i_clk];
+
+set_property -dict {PACKAGE_PIN D10  IOSTANDARD LVCMOS33 } [get_ports q]
+
+#set_property -dict {PACKAGE_PIN H5  IOSTANDARD LVCMOS33 } [get_ports q]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];
diff --git a/servant.core b/servant.core
index ea364ee..5d55d3b 100644
--- a/servant.core
+++ b/servant.core
@@ -38,6 +38,11 @@ filesets:
       - servant/servix_clock_gen.v : {file_type : verilogSource}
       - servant/servix.v : {file_type : verilogSource}
       - data/nexys_a7.xdc : {file_type : xdc}
+  arty_a7_35t:
+    files:
+      - servant/servix_clock_gen.v : {file_type : verilogSource}
+      - servant/servix.v : {file_type : verilogSource}
+      - data/arty_a7_35t.xdc : {file_type : xdc}
 targets:
   default:
     filesets : [soc]
@@ -80,6 +85,14 @@ targets:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : servix
 
+  arty_a7_35t:
+    default_tool: vivado
+    filesets : [mem_files, soc, arty_a7_35t]
+    parameters : [memfile, memsize, frequency=16]
+    tools:
+      vivado: {part : xc7a35ticsg324-1L}
+    toplevel : servix
+
   sim:
     default_tool: icarus
     filesets : [soc, servant_tb]