From 61ef8eaef9f795e2e5425f620e96c6f732a5609b Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 17 Oct 2025 17:38:00 +0200 Subject: [PATCH] Declare trap_pending before use --- rtl/serv_state.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/rtl/serv_state.v b/rtl/serv_state.v index 09e1ced..acb3014 100644 --- a/rtl/serv_state.v +++ b/rtl/serv_state.v @@ -100,6 +100,11 @@ module serv_state //valid signal for mdu assign o_mdu_valid = MDU & !o_cnt_en & init_done & i_mdu_op; + //trap_pending is only guaranteed to have correct value during the + // last cycle of the init stage + wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) | + (i_dbus_en & i_mem_misalign)); + //Prepare RF for writes when everything is ready to enter stage two // and the first stage didn't cause a misalign exception //Left shifts, SLT & Branch ops. First cycle after init @@ -218,11 +223,6 @@ module serv_state assign o_ctrl_trap = WITH_CSR & (i_e_op | i_new_irq | misalign_trap_sync); - //trap_pending is only guaranteed to have correct value during the - // last cycle of the init stage - wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) | - (i_dbus_en & i_mem_misalign)); - generate if (WITH_CSR) begin : gen_csr reg misalign_trap_sync_r;