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Replace wb_ram with servant_ram

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Olof Kindgren
2019-08-25 20:45:23 +02:00
parent d2cf7e547a
commit 65eb89323a
8 changed files with 46 additions and 296 deletions
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18
servant/servant.v
View File

@@ -107,12 +107,12 @@ serv_arbiter serv_arbiter
initial
if ($value$plusargs("firmware=%s", firmware_file)) begin
$display("Loading RAM from %0s", firmware_file);
$readmemh(firmware_file, ram.ram0.mem);
$readmemh(firmware_file, ram.mem);
end
//synthesis translate_on
`endif
wb_ram
servant_ram
#(
`ifdef SYNTHESIS
.memfile (memfile),
@@ -120,13 +120,13 @@ serv_arbiter serv_arbiter
.depth (memsize))
ram
(// Wishbone interface
.wb_clk_i (wb_clk),
.wb_adr_i (wb_mem_adr[$clog2(memsize)-1:0]),
.wb_cyc_i (wb_mem_cyc),
.wb_we_i (wb_mem_we) ,
.wb_sel_i (wb_mem_sel),
.wb_dat_i (wb_mem_dat),
.wb_dat_o (wb_mem_rdt));
.i_wb_clk (wb_clk),
.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:0]),
.i_wb_cyc (wb_mem_cyc),
.i_wb_we (wb_mem_we) ,
.i_wb_sel (wb_mem_sel),
.i_wb_dat (wb_mem_dat),
.o_wb_rdt (wb_mem_rdt));
riscv_timer riscv_timer
(.i_clk (wb_clk),

35
servant/servant_ram.v Normal file
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@@ -0,0 +1,35 @@
`default_nettype none
module servant_ram
#(//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wire i_wb_clk,
input wire [aw-1:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
output reg [31:0] o_wb_rdt);
wire [3:0] we = {4{i_wb_we & i_wb_cyc}} & i_wb_sel;
reg [31:0] mem [0:depth/4-1] /* verilator public */;
wire [aw-3:0] addr = i_wb_adr[aw-1:2];
always @(posedge i_wb_clk) begin
if (we[0]) mem[addr][7:0] <= i_wb_dat[7:0];
if (we[1]) mem[addr][15:8] <= i_wb_dat[15:8];
if (we[2]) mem[addr][23:16] <= i_wb_dat[23:16];
if (we[3]) mem[addr][31:24] <= i_wb_dat[31:24];
o_wb_rdt <= mem[addr];
end
initial
if(|memfile) begin
$display("Preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
endmodule