diff --git a/data/ac701.xdc b/data/ac701.xdc
new file mode 100644
index 0000000..ec0e813
--- /dev/null
+++ b/data/ac701.xdc
@@ -0,0 +1,11 @@
+## Clock signal
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+set_property PACKAGE_PIN P3 [get_ports sys_clk_n]
+set_property PACKAGE_PIN R3 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+
+create_clock -period 5.000 -name clk_p [get_nets sys_clk_p]
+
+## UART TX
+set_property PACKAGE_PIN U19 [get_ports q]
+set_property IOSTANDARD LVCMOS18 [get_ports q]
diff --git a/servant.core b/servant.core
index d927149..5d97f38 100644
--- a/servant.core
+++ b/servant.core
@@ -72,6 +72,12 @@ filesets:
       - servant/servix.v : {file_type : verilogSource}
       - data/arty_a7_35t.xdc : {file_type : xdc}
 
+  ac701:
+    files:
+      - servant/servix.v : {file_type : verilogSource}
+      - servant/servant_ac701.v : {file_type : verilogSource}
+      - data/ac701.xdc : {file_type : xdc}
+
   orangecrab:
     files:
       - data/orangecrab_r02.lpf : {file_type : LPF}
@@ -197,6 +203,14 @@ targets:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : servix
 
+  ac701:
+    default_tool: vivado
+    filesets : [mem_files, soc, ac701]
+    parameters : [memfile, memsize, frequency=32]
+    tools:
+      vivado: {part : xc7a200t-fbg676-2}
+    toplevel : servant_ac701
+
   orangecrab_r0.2:
     default_tool: trellis
     description : OrangeCrab R0.2
diff --git a/servant/servant_ac701.v b/servant/servant_ac701.v
new file mode 100644
index 0000000..9f8f6db
--- /dev/null
+++ b/servant/servant_ac701.v
@@ -0,0 +1,62 @@
+`default_nettype none
+module servant_ac701
+(
+   input wire  sys_clk_p,
+   input wire  sys_clk_n,
+   input wire btn,
+   output wire q);
+
+   parameter frequency = 16;
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+   parameter PLL = "NONE";
+
+   wire      wb_clk;
+   reg       wb_rst;
+   wire      clk;
+   wire      clkfb;
+   wire      locked;
+   reg       locked_r;
+
+   IBUFDS ibufds
+   (
+     .I  (sys_clk_p),
+     .IB (sys_clk_n),
+     .O  (clk)
+   );
+
+   PLLE2_BASE
+     #(.BANDWIDTH("OPTIMIZED"),
+       .CLKFBOUT_MULT(8),
+       .CLKIN1_PERIOD(5.0), //200MHz
+       .CLKOUT0_DIVIDE((frequency == 32) ? 50 : 100),
+       .DIVCLK_DIVIDE(1),
+       .STARTUP_WAIT("FALSE"))
+   PLLE2_BASE_inst
+     (.CLKOUT0(wb_clk),
+      .CLKOUT1(),
+      .CLKOUT2(),
+      .CLKOUT3(),
+      .CLKOUT4(),
+      .CLKOUT5(),
+      .CLKFBOUT(clkfb),
+      .LOCKED(locked),
+      .CLKIN1(clk),
+      .PWRDWN(1'b0),
+      .RST(1'b0),
+      .CLKFBIN(clkfb));
+
+   always @(posedge wb_clk) begin
+      locked_r <= locked;
+      wb_rst <= !locked_r;
+   end
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule