From 727bb40a8784c50b081abdcfd784a5bc7c34e40e Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sun, 14 Mar 2021 00:12:29 +0100 Subject: [PATCH] Simplify control logic for bool ops --- rtl/serv_alu.v | 2 +- rtl/serv_decode.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v index 400c181..278186b 100644 --- a/rtl/serv_alu.v +++ b/rtl/serv_alu.v @@ -39,7 +39,7 @@ module serv_alu assign o_cmp = i_cmp_eq ? result_eq : result_lt; - localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor + localparam [15:0] BOOL_LUT = 16'h8E06;//And, Or, 0, xor wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, i_op_b}]; assign o_rd = (i_rd_sel[0] & result_add) | diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v index 8bc1dc4..e7f2fa7 100644 --- a/rtl/serv_decode.v +++ b/rtl/serv_decode.v @@ -207,7 +207,7 @@ module serv_decode assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT* - assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool + assign o_alu_rd_sel[3] = funct3[2]; //Bool always @(posedge clk) begin if (i_wb_en) begin funct3 <= i_wb_rdt[14:12];