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Add support for LX9 Microboard

This commit is contained in:
Olof Kindgren
2020-05-06 20:51:55 +02:00
parent 95c5c027a1
commit 794748dac4
4 changed files with 96 additions and 0 deletions

32
servant/servant_lx9.v Normal file
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`default_nettype none
module servant_lx9
(
input wire i_clk,
input wire i_rst,
output wire o_uart_tx,
output wire q);
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
wire wb_clk;
wire wb_rst;
assign o_uart_tx = q;
servant_lx9_clock_gen
clock_gen
(.i_clk (i_clk),
.i_rst (i_rst),
.o_clk (wb_clk),
.o_rst (wb_rst));
servant
#(.memfile (memfile),
.memsize (memsize))
servant
(.wb_clk (wb_clk),
.wb_rst (wb_rst),
.q (q));
endmodule

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`default_nettype none
module servant_lx9_clock_gen
(input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
PLL_BASE
#(.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN_PERIOD(25.0), //40MHz
.CLKOUT1_DIVIDE(40), //16MHz
.DIVCLK_DIVIDE(1))
PLL_BASE_inst
(.CLKOUT1(o_clk),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN(i_clk),
.RST(i_rst),
.CLKFBIN(clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule