From 7a6d5d3fc909899e0730faf28a9a7cba370439b6 Mon Sep 17 00:00:00 2001
From: Katherine Watson <katie@radicalsemiconductor.com>
Date: Fri, 10 Nov 2023 18:05:49 -0800
Subject: [PATCH] Make serv_alu.v synthesizable with Vivado

---
 rtl/serv_alu.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v
index 2679a4a..48260be 100644
--- a/rtl/serv_alu.v
+++ b/rtl/serv_alu.v
@@ -60,7 +60,7 @@ module serv_alu
 
    assign result_slt[0] = cmp_r & i_cnt0;
    generate
-      if (W>1) assign result_slt[B:1] = '0;
+      if (W>1) assign result_slt[B:1] = {B{1'b0}};
    endgenerate
 
    assign o_rd = i_buf |