diff --git a/.github/workflows/openlane.yml b/.github/workflows/openlane.yml index aa93e12..a2225f3 100644 --- a/.github/workflows/openlane.yml +++ b/.github/workflows/openlane.yml @@ -6,7 +6,7 @@ jobs: runs-on: ubuntu-latest env: REPO : serv - VLNV : serv + VLNV : award-winning:serv:serv steps: - name: Checkout repo uses: actions/checkout@v4 @@ -15,11 +15,11 @@ jobs: - run: echo "EDALIZE_LAUNCHER=el_docker" >> $GITHUB_ENV - run: pip3 install fusesoc - run: fusesoc library add $REPO $GITHUB_WORKSPACE/$REPO - - run: fusesoc run --target=sky130 $VLNV + - run: fusesoc run --target=sky130 --work-root=openlane_work $VLNV - run: find -name *.gds - name: Store artifacts uses: actions/upload-artifact@v4 with: name: serv.gds - path: build/serv_1.3.0/sky130-openlane/runs/serv_synth_wrapper/results/finishing/serv_synth_wrapper.gds + path: openlane_work/runs/serv_synth_wrapper/results/finishing/serv_synth_wrapper.gds diff --git a/NEWS b/NEWS index b2cf95a..f0f003e 100644 --- a/NEWS +++ b/NEWS @@ -1,3 +1,16 @@ +1.4.0 2025-10-15 Olof Kindgren +====================================================== + +* Zephyr BSP: Port to Zephyr 4.0.0 +* Fix mstatus[mpp] field +* Fix misa and mstatus being triggered at the same time +* Add documentation for extension interface +* Add Subservient documentation +* Add 4-bit mode (QERV) +* Add simulation debug module +* New servant ports: Trenz Electronic TE0802 +* Make slt, branches and shifts one cycle faster + 1.3.0 2024-07-05 Olof Kindgren ====================================================== diff --git a/README.md b/README.md index fb0909b..7ca970f 100644 --- a/README.md +++ b/README.md @@ -89,7 +89,7 @@ Each of the following commands should be run from the workspace directory: If everything worked, the output should look like - INFO: Preparing ::serv:1.3.0 + INFO: Preparing award-winning:serv:serv:1.4.0 INFO: Setting up project INFO: Building simulation model diff --git a/doc/servant.rst b/doc/servant.rst index e5061bf..0a668c7 100644 --- a/doc/servant.rst +++ b/doc/servant.rst @@ -144,7 +144,7 @@ iCEstick Pin 95 is used as the GPIO output which is connected to the board's green LED. Due to this board's limited Embedded BRAM, programs with a maximum of 7168 bytes can be loaded. The default program for this board is blinky.hex. fusesoc run --target=icestick servant - iceprog build/servant_1.3.0/icestick-icestorm/servant_1.3.0.bin + iceprog build/servant_1.4.0/icestick-icestorm/servant_1.4.0.bin iCESugar ^^^^^^^^ @@ -162,7 +162,7 @@ Pin 9 is used for UART output with 57600 baud rate. fusesoc run --target=icev_wireless servant - iceprog build/servant_1.3.0/icestick-icestorm/servant_1.3.0.bin + iceprog build/servant_1.4.0/icestick-icestorm/servant_1.4.0.bin GMM7550 ^^^^^^^ @@ -181,7 +181,7 @@ Pin B1 is used for UART output with 115200 baud rate. The serial port on Kolibri fusesoc run --target=machdyne_kolibri servant - ldprog -Ks build/servant_1.3.0/machdyne_kolibri-icestorm/servant_1.3.0.bin + ldprog -Ks build/servant_1.4.0/machdyne_kolibri-icestorm/servant_1.4.0.bin MAX10 10M08 Evaluation Kit ^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -196,7 +196,7 @@ Nandland Go Board Pin 56 is used as the GPIO output which is connected to the board's LED1. Due to this board's limited Embedded BRAM, programs with a maximum of 7168 bytes can be loaded. The default program for this board is blinky.hex. fusesoc run --target=go_board servant - iceprog build/servant_1.3.0/go_board-icestorm/servant_1.3.0.bin + iceprog build/servant_1.4.0/go_board-icestorm/servant_1.4.0.bin Nexys 2 ^^^^^^^ @@ -218,7 +218,7 @@ OrangeCrab R0.2 Pin D1 is used for UART output with 115200 baud rate. fusesoc run --target=orangecrab_r0.2 servant - dfu-util -d 1209:5af0 -D build/servant_1.3.0/orangecrab_r0.2-trellis/servant_1.3.0.bit + dfu-util -d 1209:5af0 -D build/servant_1.4.0/orangecrab_r0.2-trellis/servant_1.4.0.bit PolarFire Splash Kit ^^^^^^^^^^^^^^^^^^^^ diff --git a/serv.core b/serv.core index 3746a12..7dc4167 100644 --- a/serv.core +++ b/serv.core @@ -1,6 +1,8 @@ CAPI=2: -name : ::serv:1.3.0 +name : award-winning:serv:serv:1.4.0 +description: The award-winning SERV, the world's smallest RISC-V CPU +license: ISC filesets: core: diff --git a/servant.core b/servant.core index fa641b3..0058add 100644 --- a/servant.core +++ b/servant.core @@ -1,7 +1,8 @@ CAPI=2: -name : ::servant:1.3.0 +name : award-winning:serv:servant:1.4.0 description: Simple reference system for SERV +license: ISC filesets: # Common filesets @@ -37,7 +38,7 @@ filesets: - "!tool_quartus? (servant/servant_ram.v)" - servant/servant.v file_type : verilogSource - depend : [servile, "mdu? (mdu)"] + depend : [award-winning:serv:servile, "mdu? (mdu)"] verilator_tb: files: diff --git a/servile.core b/servile.core index c4ce88e..0b6cab7 100644 --- a/servile.core +++ b/servile.core @@ -1,8 +1,8 @@ CAPI=2: -name : ::servile:1.3.0 - +name : award-winning:serv:servile:1.4.0 description: Convenience wrapper for SERV +license: ISC filesets: rtl: @@ -12,7 +12,7 @@ filesets: - servile/servile_arbiter.v - servile/servile.v file_type: verilogSource - depend : [serv] + depend : [award-winning:serv:serv] targets: default: diff --git a/serving.core b/serving.core index f80f0b6..f4ecc46 100644 --- a/serving.core +++ b/serving.core @@ -1,7 +1,8 @@ CAPI=2: -name : ::serving:1.3.0 +name : award-winning:serv:serving:1.4.0 description: SERV-based subsystem for FPGAs +license: ISC filesets: rtl: @@ -9,7 +10,7 @@ filesets: - serving/serving_ram.v - serving/serving.v file_type : verilogSource - depend : [servile] + depend : [award-winning:serv:servile] targets: default: diff --git a/verif/plugin-serv/riscof_serv.py b/verif/plugin-serv/riscof_serv.py index 938b27c..ac96e01 100644 --- a/verif/plugin-serv/riscof_serv.py +++ b/verif/plugin-serv/riscof_serv.py @@ -8,7 +8,7 @@ logger = logging.getLogger() class serv(pluginTemplate): __model__ = "serv" - __version__ = "1.3.0" + __version__ = "1.4.0" def __init__(self, *args, **kwargs): sclass = super().__init__(*args, **kwargs) @@ -39,7 +39,7 @@ class serv(pluginTemplate): utils.shellCommand(add_mdu).run() build_serv = 'fusesoc run --target=verilator_tb --flag=mdu\ - --build --build-root=servant_test servant\ + --build --work-root=servant_test award-winning:serv:servant\ --memsize=8388608 --compressed=1' utils.shellCommand(build_serv).run() @@ -76,9 +76,7 @@ class serv(pluginTemplate): #The behavior of --build-root in FuseSoC has changed since version 2.2.1 #Check first for executable model in the new location and else fall back #to the old one - exe = 'servant_test/verilator_tb/Vservant_sim' - if not os.path.exists(exe): - exe = 'servant_test/servant_1.3.0/verilator_tb/Vservant_sim' + exe = 'servant_test/Vservant_sim' sigdump_run = [exe, "+timeout=1000000000",