From 7f16f17ca5fd426f6078dee277481c4a03c5a68c Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Wed, 19 Feb 2020 10:02:48 +0100
Subject: [PATCH] Optimize CSR immediate handling

---
 rtl/serv_decode.v | 4 ++++
 rtl/serv_state.v  | 5 +----
 rtl/serv_top.v    | 5 ++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v
index 25357c9..fad5f8a 100644
--- a/rtl/serv_decode.v
+++ b/rtl/serv_decode.v
@@ -52,6 +52,7 @@ module serv_decode
    output wire 	     o_csr_mcause_en,
    output wire [1:0] o_csr_source,
    output wire 	     o_csr_d_sel,
+   output wire 	     o_csr_imm,
    //To top
    output wire 	     o_imm,
    output wire 	     o_op_b_source,
@@ -151,6 +152,7 @@ module serv_decode
 
    assign o_csr_source = funct3[1:0];
    assign o_csr_d_sel = funct3[2];
+   assign o_csr_imm = o_rf_rs1_addr[0];
 
    assign o_csr_addr = (op26 & !op20) ? CSR_MSCRATCH :
 		       (op26 & !op21) ? CSR_MEPC :
@@ -209,6 +211,8 @@ module serv_decode
 	 imm30_25    <= {m2[1] ? imm7 : m2[0] ? signbit : imm19_12_20[0], imm30_25[5:1]};
 	 imm24_20    <= {imm30_25[0], imm24_20[4:1]};
 	 imm11_7     <= {imm30_25[0], imm11_7[4:1]};
+	 if (csr_op & o_csr_d_sel)
+	   o_rf_rs1_addr <= {1'b0,o_rf_rs1_addr[4:1]};
       end
    end
 
diff --git a/rtl/serv_state.v b/rtl/serv_state.v
index af67314..859b4d0 100644
--- a/rtl/serv_state.v
+++ b/rtl/serv_state.v
@@ -18,7 +18,6 @@ module serv_state
    input wire 	     i_slt_op,
    input wire 	     i_e_op,
    input wire 	     i_rd_op,
-   input wire [4:0]  i_rs1_addr,
    output wire 	     o_init,
    output wire 	     o_cnt_en,
    output reg [4:0]  o_cnt,
@@ -33,8 +32,7 @@ module serv_state
    output wire [1:0] o_mem_bytecnt,
    input wire 	     i_mem_misalign,
    output reg 	     o_cnt_done,
-   output wire 	     o_bufreg_hold,
-   output wire 	     o_csr_imm);
+   output wire 	     o_bufreg_hold);
 
    localparam [1:0]
      IDLE     = 2'd0,
@@ -49,7 +47,6 @@ module serv_state
    //Update PC in RUN or TRAP states
    assign o_ctrl_pc_en  = o_cnt_en & !o_init;
 
-   assign o_csr_imm = (o_cnt < 5) ? i_rs1_addr[o_cnt[2:0]] : 1'b0;
    assign o_alu_shamt_en = (o_cnt < 5) & o_init;
 
    assign o_mem_bytecnt = o_cnt[4:3];
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index 4941e3d..42cb5c3 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -163,7 +163,6 @@ module serv_top
       .i_slt_op       (slt_op),
       .i_e_op         (e_op),
       .i_rd_op        (rd_op),
-      .i_rs1_addr     (rs1_addr),
       .o_init         (init),
       .o_cnt_en       (cnt_en),
       .o_cnt          (cnt),
@@ -178,8 +177,7 @@ module serv_top
       .i_alu_sh_done  (alu_sh_done),
       .o_dbus_cyc     (o_dbus_cyc),
       .o_mem_bytecnt  (mem_bytecnt),
-      .i_mem_misalign (mem_misalign),
-      .o_csr_imm      (csr_imm));
+      .i_mem_misalign (mem_misalign));
 
    wire 	bufreg_clr_lsb;
 
@@ -237,6 +235,7 @@ module serv_top
       .o_csr_mcause_en    (csr_mcause_en),
       .o_csr_source       (csr_source),
       .o_csr_d_sel        (csr_d_sel),
+      .o_csr_imm          (csr_imm),
       //To top
       .o_imm              (imm),
       .o_rd_csr_en        (rd_csr_en),