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Use servile as base for serving

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Olof Kindgren
2024-02-06 15:30:55 +01:00
parent 970c6fddca
commit 88a4711593
8 changed files with 176 additions and 337 deletions
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237
serving/serving.v
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@@ -34,35 +34,13 @@ module serving
parameter memfile = "";
parameter memsize = 8192;
parameter sim = 1'b0;
parameter RESET_STRATEGY = "NONE";
parameter WITH_CSR = 1;
localparam regs = 32+WITH_CSR*4;
localparam rf_width = 8;
localparam aw = $clog2(memsize);
wire [31:0] wb_ibus_adr;
wire wb_ibus_stb;
wire [31:0] wb_ibus_rdt;
wire wb_ibus_ack;
wire [31:0] wb_dbus_adr;
wire [31:0] wb_dbus_dat;
wire [3:0] wb_dbus_sel;
wire wb_dbus_we;
wire wb_dbus_stb;
wire [31:0] wb_dbus_rdt;
wire wb_dbus_ack;
wire [31:0] wb_dmem_adr;
wire [31:0] wb_dmem_dat;
wire [3:0] wb_dmem_sel;
wire wb_dmem_we;
wire wb_dmem_stb;
wire [31:0] wb_dmem_rdt;
wire wb_dmem_ack;
wire [31:0] wb_mem_adr;
wire [31:0] wb_mem_dat;
wire [3:0] wb_mem_sel;
@@ -71,65 +49,19 @@ module serving
wire [31:0] wb_mem_rdt;
wire wb_mem_ack;
wire [6+WITH_CSR:0] waddr;
wire [rf_width-1:0] wdata;
wire wen;
wire [6+WITH_CSR:0] raddr;
wire [rf_width-1:0] rdata;
wire [6+WITH_CSR:0] rf_waddr;
wire [rf_width-1:0] rf_wdata;
wire rf_wen;
wire [6+WITH_CSR:0] rf_raddr;
wire [rf_width-1:0] rf_rdata;
wire rf_ren;
wire [aw-1:0] rf_waddr = ~{{aw-2-5-WITH_CSR{1'b0}},waddr};
wire [aw-1:0] rf_raddr = ~{{aw-2-5-WITH_CSR{1'b0}},raddr};
serving_arbiter arbiter
(.i_wb_cpu_dbus_adr (wb_dmem_adr),
.i_wb_cpu_dbus_dat (wb_dmem_dat),
.i_wb_cpu_dbus_sel (wb_dmem_sel),
.i_wb_cpu_dbus_we (wb_dmem_we ),
.i_wb_cpu_dbus_stb (wb_dmem_stb),
.o_wb_cpu_dbus_rdt (wb_dmem_rdt),
.o_wb_cpu_dbus_ack (wb_dmem_ack),
.i_wb_cpu_ibus_adr (wb_ibus_adr),
.i_wb_cpu_ibus_stb (wb_ibus_stb),
.o_wb_cpu_ibus_rdt (wb_ibus_rdt),
.o_wb_cpu_ibus_ack (wb_ibus_ack),
.o_wb_mem_adr (wb_mem_adr),
.o_wb_mem_dat (wb_mem_dat),
.o_wb_mem_sel (wb_mem_sel),
.o_wb_mem_we (wb_mem_we ),
.o_wb_mem_stb (wb_mem_stb),
.i_wb_mem_rdt (wb_mem_rdt),
.i_wb_mem_ack (wb_mem_ack));
serving_mux mux
(.i_clk (i_clk),
.i_rst (i_rst & (RESET_STRATEGY != "NONE")),
.i_wb_cpu_adr (wb_dbus_adr),
.i_wb_cpu_dat (wb_dbus_dat),
.i_wb_cpu_sel (wb_dbus_sel),
.i_wb_cpu_we (wb_dbus_we),
.i_wb_cpu_stb (wb_dbus_stb),
.o_wb_cpu_rdt (wb_dbus_rdt),
.o_wb_cpu_ack (wb_dbus_ack),
.o_wb_mem_adr (wb_dmem_adr),
.o_wb_mem_dat (wb_dmem_dat),
.o_wb_mem_sel (wb_dmem_sel),
.o_wb_mem_we (wb_dmem_we),
.o_wb_mem_stb (wb_dmem_stb),
.i_wb_mem_rdt (wb_dmem_rdt),
.i_wb_mem_ack (wb_dmem_ack),
.o_wb_ext_adr (o_wb_adr),
.o_wb_ext_dat (o_wb_dat),
.o_wb_ext_sel (o_wb_sel),
.o_wb_ext_we (o_wb_we),
.o_wb_ext_stb (o_wb_stb),
.i_wb_ext_rdt (i_wb_rdt),
.i_wb_ext_ack (i_wb_ack));
wire [$clog2(memsize)-1:0] sram_waddr;
wire [rf_width-1:0] sram_wdata;
wire sram_wen;
wire [$clog2(memsize)-1:0] sram_raddr;
wire [rf_width-1:0] sram_rdata;
wire sram_ren;
serving_ram
#(.memfile (memfile),
@@ -137,11 +69,35 @@ module serving
ram
(// Wishbone interface
.i_clk (i_clk),
.i_waddr (sram_waddr),
.i_wdata (sram_wdata),
.i_wen (sram_wen),
.i_raddr (sram_raddr),
.o_rdata (sram_rdata)/*,
.i_ren (rf_ren)*/);
servile_rf_mem_if
#(.depth (memsize),
.rf_regs (regs))
rf_mem_if
(// Wishbone interface
.i_clk (i_clk),
.i_rst (i_rst),
.i_waddr (rf_waddr),
.i_wdata (wdata),
.i_wen (wen),
.i_wdata (rf_wdata),
.i_wen (rf_wen),
.i_raddr (rf_raddr),
.o_rdata (rdata),
.o_rdata (rf_rdata),
.i_ren (rf_ren),
.o_sram_waddr (sram_waddr),
.o_sram_wdata (sram_wdata),
.o_sram_wen (sram_wen),
.o_sram_raddr (sram_raddr),
.i_sram_rdata (sram_rdata),
.o_sram_ren (sram_ren),
.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
.i_wb_stb (wb_mem_stb),
.i_wb_we (wb_mem_we) ,
@@ -150,94 +106,41 @@ module serving
.o_wb_rdt (wb_mem_rdt),
.o_wb_ack (wb_mem_ack));
localparam RF_L2W = $clog2(rf_width);
wire rf_wreq;
wire rf_rreq;
wire [$clog2(regs)-1:0] wreg0;
wire [$clog2(regs)-1:0] wreg1;
wire wen0;
wire wen1;
wire wdata0;
wire wdata1;
wire [$clog2(regs)-1:0] rreg0;
wire [$clog2(regs)-1:0] rreg1;
wire rf_ready;
wire rdata0;
wire rdata1;
serv_rf_ram_if
#(.width (rf_width),
servile
#(.reset_pc (32'h0000_0000),
.reset_strategy (RESET_STRATEGY),
.csr_regs (WITH_CSR*4))
rf_ram_if
(.i_clk (i_clk),
.i_rst (i_rst),
.i_wreq (rf_wreq),
.i_rreq (rf_rreq),
.o_ready (rf_ready),
.i_wreg0 (wreg0),
.i_wreg1 (wreg1),
.i_wen0 (wen0),
.i_wen1 (wen1),
.i_wdata0 (wdata0),
.i_wdata1 (wdata1),
.i_rreg0 (rreg0),
.i_rreg1 (rreg1),
.o_rdata0 (rdata0),
.o_rdata1 (rdata1),
.o_waddr (waddr),
.o_wdata (wdata),
.o_wen (wen),
.o_raddr (raddr),
.o_ren (),
.i_rdata (rdata));
serv_top
#(.RESET_PC (32'h0000_0000),
.RESET_STRATEGY (RESET_STRATEGY),
.WITH_CSR (WITH_CSR))
cpu
.sim (sim),
.with_csr (WITH_CSR))
servile
(
.clk (i_clk),
.i_clk (i_clk),
.i_rst (i_rst),
.i_timer_irq (i_timer_irq),
//Memory interface
.o_wb_mem_adr (wb_mem_adr),
.o_wb_mem_dat (wb_mem_dat),
.o_wb_mem_sel (wb_mem_sel),
.o_wb_mem_we (wb_mem_we),
.o_wb_mem_stb (wb_mem_stb),
.i_wb_mem_rdt (wb_mem_rdt),
.i_wb_mem_ack (wb_mem_ack),
//Extension interface
.o_wb_ext_adr (o_wb_adr),
.o_wb_ext_dat (o_wb_dat),
.o_wb_ext_sel (o_wb_sel),
.o_wb_ext_we (o_wb_we),
.o_wb_ext_stb (o_wb_stb),
.i_wb_ext_rdt (i_wb_rdt),
.i_wb_ext_ack (i_wb_ack),
//RF IF
.o_rf_rreq (rf_rreq),
.o_rf_wreq (rf_wreq),
.i_rf_ready (rf_ready),
.o_wreg0 (wreg0),
.o_wreg1 (wreg1),
.o_wen0 (wen0),
.o_wen1 (wen1),
.o_wdata0 (wdata0),
.o_wdata1 (wdata1),
.o_rreg0 (rreg0),
.o_rreg1 (rreg1),
.i_rdata0 (rdata0),
.i_rdata1 (rdata1),
.o_rf_waddr (rf_waddr),
.o_rf_wdata (rf_wdata),
.o_rf_wen (rf_wen),
.o_rf_raddr (rf_raddr),
.o_rf_ren (rf_ren),
.i_rf_rdata (rf_rdata));
//Instruction bus
.o_ibus_adr (wb_ibus_adr),
.o_ibus_cyc (wb_ibus_stb),
.i_ibus_rdt (wb_ibus_rdt),
.i_ibus_ack (wb_ibus_ack),
//Data bus
.o_dbus_adr (wb_dbus_adr),
.o_dbus_dat (wb_dbus_dat),
.o_dbus_sel (wb_dbus_sel),
.o_dbus_we (wb_dbus_we),
.o_dbus_cyc (wb_dbus_stb),
.i_dbus_rdt (wb_dbus_rdt),
.i_dbus_ack (wb_dbus_ack),
.o_ext_funct3 (),
.i_ext_ready (1'b0),
.i_ext_rd (32'd0),
.o_ext_rs1 (),
.o_ext_rs2 (),
.o_mdu_valid ());
endmodule