From 88ffe617f5634d550d5c256660f0fcb2f8abc3f2 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Mon, 12 Oct 2020 14:45:05 +0200
Subject: [PATCH] WIP: Quickfeather support

FIXME:
Verify clock/reset
---
 data/eos_s3.pcf      |  2 ++
 data/eos_s3.sdc      |  1 +
 servant.core         | 18 ++++++++++++++++++
 servant/servant_qf.v | 42 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 63 insertions(+)
 create mode 100644 data/eos_s3.pcf
 create mode 100644 data/eos_s3.sdc
 create mode 100644 servant/servant_qf.v

diff --git a/data/eos_s3.pcf b/data/eos_s3.pcf
new file mode 100644
index 0000000..66da1db
--- /dev/null
+++ b/data/eos_s3.pcf
@@ -0,0 +1,2 @@
+set_io i_rst_n 62
+set_io o_uart_tx 39
diff --git a/data/eos_s3.sdc b/data/eos_s3.sdc
new file mode 100644
index 0000000..15369b7
--- /dev/null
+++ b/data/eos_s3.sdc
@@ -0,0 +1 @@
+create_clock -period 83 i_clk
diff --git a/servant.core b/servant.core
index bd2e6d6..c4b5fec 100644
--- a/servant.core
+++ b/servant.core
@@ -116,6 +116,12 @@ filesets:
       - servant/servis.v : {file_type : verilogSource}
       - data/pipistrello.ucf : {file_type : UCF}
 
+  qf:
+    files:
+      - data/eos_s3.pcf : {file_type : PCF}
+      - data/eos_s3.sdc : {file_type : SDC}
+      - servant/servant_qf.v : {file_type : verilogSource}
+
   ulx3s:
     files:
       - data/ulx3s.lpf : {file_type : LPF}
@@ -181,6 +187,18 @@ targets:
         device : EP4CE22F17C6
     toplevel: servive
 
+  quickfeather:
+    default_tool : symbiflow
+    filesets : [mem_files, soc, qf]
+    parameters : [memfile, memsize]
+    tools:
+      symbiflow:
+        vendor : quicklogic
+        package : PU64
+        part : ql-eos-s3
+        pnr : vtr
+    toplevel: servant_qf
+
   icebreaker:
     default_tool : icestorm
     filesets : [mem_files, soc, service, icebreaker]
diff --git a/servant/servant_qf.v b/servant/servant_qf.v
new file mode 100644
index 0000000..f0ad000
--- /dev/null
+++ b/servant/servant_qf.v
@@ -0,0 +1,42 @@
+module servant_qf
+  (
+   input wire  i_rst_n,
+   output wire o_uart_tx);
+
+   reg 	       rst_r;
+
+   wire        i_clk;
+   wire        i_rst;
+   wire        clk;
+//   wire        rst;
+
+//   parameter memfile = "zephyr_hello.hex";
+   parameter memfile = "blinky.hex";
+   parameter memsize = 2048;
+
+   qlal4s3b_cell_macro u_qlal4s3b_cell_macro
+     (
+      .Sys_Clk0     (i_clk),
+      .Sys_Clk0_Rst (i_rst),
+      .Sys_Clk1     (),
+      .Sys_Clk1_Rst ());
+
+   gclkbuff u_gclkbuff_clock0 (.A(i_clk), .Z(clk));
+//   gclkbuff u_gclkbuff_reset0 (.A(i_rst), .Z(rst));
+
+   wire        o_uart_tx = q;
+
+   reg 	       rst;
+
+   always @(posedge clk)
+     rst <= !i_rst_n;
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (clk),
+      .wb_rst (rst),
+      .q      (q));
+
+endmodule