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Stop using states in logic expressions

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Olof Kindgren
2020-04-04 23:44:29 +02:00
parent 9a8dcde030
commit 8dd75fa752
1 changed files with 2 additions and 2 deletions
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4
rtl/serv_state.v
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@@ -62,7 +62,7 @@ module serv_state
reg stage_two_pending; reg stage_two_pending;
assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !i_mem_misalign; assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign;
wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign); wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign);
@@ -90,7 +90,7 @@ module serv_state
o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2]; o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2];
//Need a strobe for the first cycle in the IDLE state after INIT //Need a strobe for the first cycle in the IDLE state after INIT
stage_two_req <= o_cnt_done & (state == INIT); stage_two_req <= o_cnt_done & o_init;
if (i_rf_ready && !o_cnt_en) if (i_rf_ready && !o_cnt_en)
if (i_e_op | o_pending_irq | (stage_two_pending & trap_pending)) if (i_e_op | o_pending_irq | (stage_two_pending & trap_pending))