diff --git a/rtl/serv_rf_if.v b/rtl/serv_rf_if.v
index 81d4c85..4394e85 100644
--- a/rtl/serv_rf_if.v
+++ b/rtl/serv_rf_if.v
@@ -1,49 +1,52 @@
 `default_nettype none
 module serv_rf_if
-  #(parameter WITH_CSR = 1)
+  #(parameter WITH_CSR = 1,
+    parameter W = 1,
+    parameter B = W-1
+  )
   (//RF Interface
    input wire 		      i_cnt_en,
    output wire [4+WITH_CSR:0] o_wreg0,
    output wire [4+WITH_CSR:0] o_wreg1,
    output wire 		      o_wen0,
    output wire 		      o_wen1,
-   output wire 		      o_wdata0,
-   output wire 		      o_wdata1,
+   output wire [B:0]  o_wdata0,
+   output wire [B:0]  o_wdata1,
    output wire [4+WITH_CSR:0] o_rreg0,
    output wire [4+WITH_CSR:0] o_rreg1,
-   input wire 		      i_rdata0,
-   input wire 		      i_rdata1,
+   input wire  [B:0] i_rdata0,
+   input wire  [B:0] i_rdata1,
 
    //Trap interface
    input wire 		      i_trap,
    input wire 		      i_mret,
-   input wire 		      i_mepc,
-   input wire 		      i_mtval_pc,
-   input wire 		      i_bufreg_q,
-   input wire 		      i_bad_pc,
-   output wire 		      o_csr_pc,
+   input wire [B:0] i_mepc,
+   input wire                      i_mtval_pc,
+   input wire [B:0] i_bufreg_q,
+   input wire [B:0] i_bad_pc,
+   output wire [B:0] o_csr_pc,
    //CSR interface
    input wire 		      i_csr_en,
    input wire [1:0] 	      i_csr_addr,
-   input wire 		      i_csr,
-   output wire 		      o_csr,
+   input wire [B:0] i_csr,
+   output wire [B:0] o_csr,
    //RD write port
    input wire 		      i_rd_wen,
    input wire [4:0] 	      i_rd_waddr,
-   input wire 		      i_ctrl_rd,
-   input wire 		      i_alu_rd,
+   input wire [B:0] i_ctrl_rd,
+   input wire [B:0] i_alu_rd,
    input wire 		      i_rd_alu_en,
-   input wire 		      i_csr_rd,
+   input wire [B:0] i_csr_rd,
    input wire 		      i_rd_csr_en,
-   input wire 		      i_mem_rd,
+   input wire [B:0] i_mem_rd,
    input wire 		      i_rd_mem_en,
 
    //RS1 read port
    input wire [4:0] 	      i_rs1_raddr,
-   output wire 		      o_rs1,
+   output wire [B:0] o_rs1,
    //RS2 read port
    input wire [4:0] 	      i_rs2_raddr,
-   output wire 		      o_rs2);
+   output wire [B:0] o_rs2);
 
 
    /*
@@ -54,12 +57,13 @@ module serv_rf_if
 
    generate
    if (|WITH_CSR) begin : gen_csr
-   wire 	     rd = (i_ctrl_rd ) |
-			  (i_alu_rd & i_rd_alu_en) |
-			  (i_csr_rd & i_rd_csr_en) |
-			  (i_mem_rd & i_rd_mem_en);
+   wire [B:0] rd =
+       {W{i_rd_alu_en}} & i_alu_rd |
+       {W{i_rd_csr_en}} & i_csr_rd |
+       {W{i_rd_mem_en}} & i_mem_rd |
+                       i_ctrl_rd;
 
-   wire 	     mtval = i_mtval_pc ? i_bad_pc : i_bufreg_q;
+   wire [B:0]  mtval = i_mtval_pc ? i_bad_pc : i_bufreg_q;
 
    assign 	     o_wdata0 = i_trap ? mtval  : rd;
    assign	     o_wdata1 = i_trap ? i_mepc : i_csr;
@@ -116,16 +120,16 @@ module serv_rf_if
 
    assign o_rs1 = i_rdata0;
    assign o_rs2 = i_rdata1;
-   assign o_csr = i_rdata1 & i_csr_en;
+   assign o_csr = i_rdata1 & {W{i_csr_en}};
    assign o_csr_pc = i_rdata1;
 
    end else begin : gen_no_csr
-      wire 	     rd = (i_ctrl_rd ) |
-			  (i_alu_rd & i_rd_alu_en) |
-			  (i_mem_rd & i_rd_mem_en);
+      wire [B:0] rd = (i_ctrl_rd) |
+          i_alu_rd  & {W{i_rd_alu_en}} |
+          i_mem_rd  & {W{i_rd_mem_en}};
 
       assign 	     o_wdata0 = rd;
-      assign	     o_wdata1 = 1'b0;
+      assign	     o_wdata1 = {W{1'b0}};
 
       assign o_wreg0 = i_rd_waddr;
       assign o_wreg1 = 5'd0;
@@ -142,8 +146,8 @@ module serv_rf_if
 
       assign o_rs1 = i_rdata0;
       assign o_rs2 = i_rdata1;
-      assign o_csr = 1'b0;
-      assign o_csr_pc = 1'b0;
+      assign o_csr = {W{1'b0}};
+      assign o_csr_pc = {W{1'b0}};
    end // else: !if(WITH_CSR)
    endgenerate
 endmodule