diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v
index 1e3a637..14bc21d 100644
--- a/rtl/serv_decode.v
+++ b/rtl/serv_decode.v
@@ -33,10 +33,6 @@ module serv_decode
    output wire 	     o_alu_sh_signed,
    output wire 	     o_alu_sh_right,
    output wire [3:0] o_alu_rd_sel,
-   //To RF
-   output reg [4:0]  o_rf_rd_addr,
-   output reg [4:0]  o_rf_rs1_addr,
-   output reg [4:0]  o_rf_rs2_addr,
    //To mem IF
    output wire 	     o_mem_signed,
    output wire 	     o_mem_word,
@@ -115,12 +111,12 @@ module serv_decode
    //False for STORE, BRANCH, MISC-MEM
    assign o_rd_op = (opcode[2] |
 		     (!opcode[2] & opcode[4] & opcode[0]) |
-		     (!opcode[2] & !opcode[3] & !opcode[0])) & (|o_rf_rd_addr);
+		     (!opcode[2] & !opcode[3] & !opcode[0]));
 
    //True for sub, sll*, b*, slt*
    //False for add*, sr*
    assign o_alu_sub = (!funct3[2] & (funct3[0] | (opcode[3] & imm30))) | funct3[1] | opcode[4];
-   
+
 
    /*
     300 0_000 mstatus RWSC
@@ -183,9 +179,6 @@ module serv_decode
    assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool
    always @(posedge clk) begin
       if (i_wb_en) begin
-         o_rf_rd_addr  <= i_wb_rdt[11:7];
-         o_rf_rs1_addr <= i_wb_rdt[19:15];
-         o_rf_rs2_addr <= i_wb_rdt[24:20];
          funct3        <= i_wb_rdt[14:12];
          imm30         <= i_wb_rdt[30];
          opcode        <= i_wb_rdt[6:2];
diff --git a/rtl/serv_immdec.v b/rtl/serv_immdec.v
index 974967d..1a7c5b6 100644
--- a/rtl/serv_immdec.v
+++ b/rtl/serv_immdec.v
@@ -2,7 +2,7 @@
 module serv_immdec
   (
    input wire 	     i_clk,
-   //Input   
+   //Input
    input wire 	     i_cnt_en,
    input wire 	     i_csr_imm_en,
    output wire 	     o_csr_imm,
@@ -10,6 +10,10 @@ module serv_immdec
    input wire 	     i_wb_en,
    input wire 	     i_cnt_done,
    input wire [3:0]  i_ctrl,
+   //To RF
+   output reg [4:0]  o_rf_rd_addr,
+   output reg [4:0]  o_rf_rs1_addr,
+   output reg [4:0]  o_rf_rs2_addr,
    output wire 	     o_imm);
 
    reg 	      signbit;
@@ -32,6 +36,10 @@ module serv_immdec
 	 imm30_25    <= i_wb_rdt[30:25];
 	 imm24_20    <= i_wb_rdt[24:20];
 	 imm11_7     <= i_wb_rdt[11:7];
+
+         o_rf_rd_addr  <= i_wb_rdt[11:7];
+         o_rf_rs1_addr <= i_wb_rdt[19:15];
+         o_rf_rs2_addr <= i_wb_rdt[24:20];
       end
       if (i_cnt_en) begin
 	 imm19_12_20 <= {i_ctrl[3] ? signbit : imm24_20[0], imm19_12_20[8:1]};
@@ -40,5 +48,5 @@ module serv_immdec
 	 imm24_20    <= {imm30_25[0], imm24_20[4:1]};
 	 imm11_7     <= {imm30_25[0], imm11_7[4:1]};
       end
-   end   
+   end
 endmodule
diff --git a/rtl/serv_rf_if.v b/rtl/serv_rf_if.v
index b26e75f..2160150 100644
--- a/rtl/serv_rf_if.v
+++ b/rtl/serv_rf_if.v
@@ -50,6 +50,8 @@ module serv_rf_if
     ********** Write side ***********
     */
 
+   wire 	     rd_wen = i_rd_wen & (|i_rd_waddr);
+
    generate
    if (WITH_CSR) begin
    wire 	     rd = (i_ctrl_rd ) |
@@ -71,7 +73,7 @@ module serv_rf_if
    assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr};
    assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC}  : {4'b1000,i_csr_addr};
 
-   assign       o_wen0 = i_trap | i_rd_wen;
+   assign       o_wen0 = i_trap | rd_wen;
    assign       o_wen1 = i_trap | i_csr_en;
 
    /*
@@ -105,7 +107,7 @@ module serv_rf_if
       assign o_wreg0 = i_rd_waddr;
       assign o_wreg1 = 5'd0;
 
-      assign       o_wen0 =i_rd_wen;
+      assign       o_wen0 = rd_wen;
       assign       o_wen1 = 1'b0;
 
    /*
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index e7fc9c7..57b0642 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -233,10 +233,6 @@ module serv_top
       .o_alu_sh_signed    (alu_sh_signed),
       .o_alu_sh_right     (alu_sh_right),
       .o_alu_rd_sel       (alu_rd_sel),
-      //To RF
-      .o_rf_rd_addr       (rd_addr),
-      .o_rf_rs1_addr      (rs1_addr),
-      .o_rf_rs2_addr      (rs2_addr),
       //To mem IF
       .o_mem_cmd          (o_dbus_we),
       .o_mem_signed       (mem_signed),
@@ -266,6 +262,10 @@ module serv_top
       .i_wb_en    (o_ibus_cyc & i_ibus_ack),
       .i_ctrl     (immdec_ctrl),
       .i_cnt_done (cnt_done),
+      //To RF
+      .o_rf_rd_addr       (rd_addr),
+      .o_rf_rs1_addr      (rs1_addr),
+      .o_rf_rs2_addr      (rs2_addr),
       .o_imm      (imm));
 
    serv_bufreg bufreg
@@ -462,10 +462,10 @@ module serv_top
         rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]};
       if (cnt_done & ctrl_pc_en) begin
          rvfi_pc_rdata <= pc;
-	 if (!rd_en)
+	 if (!(rd_en & (|rd_addr))) begin
 	   rvfi_rd_addr <= 5'd0;
-	 if (!rd_en | !(|rd_addr))
 	   rvfi_rd_wdata <= 32'd0;
+	 end
       end
       rvfi_trap <= trap;
       if (rvfi_valid) begin