From 94c7dab38dcd7f67b841d8379b7a5a747e1d913a Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Thu, 22 Nov 2018 13:00:27 +0100
Subject: [PATCH] Addapt compliance_test printing to new signature format

---
 README.md                           | 6 ++++--
 riscv-target/serv/compliance_test.h | 4 ++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index 699d23c..188ec8e 100644
--- a/README.md
+++ b/README.md
@@ -50,7 +50,7 @@ Build the verilator model (if not already done)
 
 Download the tests repo
 
-`cd $SERV && git clone https://github.com/olofk/riscv-compliance`
+`cd $SERV && git clone https://github.com/riscv/riscv-compliance`
 
 Run the compliance tests
 
@@ -59,7 +59,9 @@ Run the compliance tests
 Run on hardware
 ---------------
 
-Only supported so far is a LED blink hack for TinyFPGA BX
+Only supported so far is a single threaded hello world on TinyFPGA BX
+
+Pin B3 is used for UART output with 57600 baud rate.
 
     cd $SERV/workspace
     fusesoc run --target=tinyfpga_bx serv
diff --git a/riscv-target/serv/compliance_test.h b/riscv-target/serv/compliance_test.h
index 796d485..512793b 100644
--- a/riscv-target/serv/compliance_test.h
+++ b/riscv-target/serv/compliance_test.h
@@ -17,7 +17,7 @@ la a0, data_begin;	 \
         li a2, 0x80000000; \
 complience_halt_loop: \
         beq a0, a1, complience_halt_break; \
-        addi a3, a0, 16; \
+        addi a3, a0, 4; \
 complience_halt_loop2: \
         addi a3, a3, -1; \
 	\
@@ -40,7 +40,7 @@ notLetter2: \
         addi a5, a5, 0x30; \
         sw a5, 0 (a2); \
         bne a0, a3,complience_halt_loop2;  \
-        addi a0, a0, 16; \
+        addi a0, a0, 4; \
 	\
         li a4, '\n'; \
         sw a4, 0 (a2); \