From 95c5c027a1bb52054df4daa8f3fa3106e0294b33 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Wed, 6 May 2020 20:10:13 +0200
Subject: [PATCH] Add Saanlima pipistrello spartan6 LX45

---
 README.md                  |  8 ++++++++
 data/pipistrello.ucf       | 12 ++++++++++++
 servant.core               | 19 +++++++++++++++++++
 servant/servis.v           | 28 ++++++++++++++++++++++++++++
 servant/servis_clock_gen.v | 34 ++++++++++++++++++++++++++++++++++
 5 files changed, 101 insertions(+)
 create mode 100644 data/pipistrello.ucf
 create mode 100644 servant/servis.v
 create mode 100644 servant/servis_clock_gen.v

diff --git a/README.md b/README.md
index b312369..99f4eba 100644
--- a/README.md
+++ b/README.md
@@ -107,6 +107,14 @@ blinky.hex change D10 to H5 (led[4]) in data/arty_a7_35t.xdc).
     cd $SERV/workspace
     fusesoc run --target=arty_a7_35t servant
 
+### Saanlima Pipistrello (Spartan6 LX45)
+
+Pin A10 (usb_data<1>) is used for UART output with 57600 baud rate (to use
+blinky.hex change A10 to V16 (led[0]) in data/pipistrello.ucf).
+
+    cd $SERV/workspace
+    fusesoc run --target=pipistrello servant
+
 ### Alhambra II
 
 Pin 61 is used for UART output with 38400 baud rate (note that it works with non-standard 43200 value too). This pin is connected to a FT2232H chip in board, that manages the communications between the FPGA and the computer.
diff --git a/data/pipistrello.ucf b/data/pipistrello.ucf
new file mode 100644
index 0000000..a1fe990
--- /dev/null
+++ b/data/pipistrello.ucf
@@ -0,0 +1,12 @@
+CONFIG VCCAUX=3.3;
+
+NET i_clk LOC = H17 | IOSTANDARD = LVTTL;
+
+NET i_clk TNM_NET = i_clk;
+TIMESPEC TS_USER_CLOCK = PERIOD i_clk 50000 kHz;
+
+
+# uart tx
+NET q LOC = A10 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+# led0
+#NET q LOC = V16 | IOSTANDARD = LVCMOS33;
diff --git a/servant.core b/servant.core
index 81fba29..a08d317 100644
--- a/servant.core
+++ b/servant.core
@@ -58,6 +58,12 @@ filesets:
       - servant/servix.v : {file_type : verilogSource}
       - data/arty_a7_35t.xdc : {file_type : xdc}
 
+  pipistrello:
+    files:
+      - servant/servis_clock_gen.v : {file_type : verilogSource}
+      - servant/servis.v : {file_type : verilogSource}
+      - data/pipistrello.ucf : {file_type : UCF}
+
   ulx3s:
     files:
       - data/ulx3s.lpf : {file_type : LPF}
@@ -149,6 +155,19 @@ targets:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : servix
 
+  pipistrello:
+    default_tool: ise
+    description : Saanlima pipistrello
+    filesets : [mem_files, soc, pipistrello]
+    parameters : [memfile, memsize]
+    tools:
+      ise:
+        family  : Spartan6
+        device  : xc6slx45
+        package : csg324
+        speed   : -3
+    toplevel : servis
+
   sim:
     default_tool: icarus
     filesets : [soc, servant_tb]
diff --git a/servant/servis.v b/servant/servis.v
new file mode 100644
index 0000000..f601d31
--- /dev/null
+++ b/servant/servis.v
@@ -0,0 +1,28 @@
+`default_nettype none
+module servis
+(
+ input wire  i_clk,
+ output wire q);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+   parameter PLL = "NONE";
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   servis_clock_gen
+   clock_gen
+     (.i_clk (i_clk),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule
diff --git a/servant/servis_clock_gen.v b/servant/servis_clock_gen.v
new file mode 100644
index 0000000..a8b9067
--- /dev/null
+++ b/servant/servis_clock_gen.v
@@ -0,0 +1,34 @@
+`default_nettype none
+module servis_clock_gen
+  (input wire  i_clk,
+   output wire o_clk,
+   output reg  o_rst);
+
+   wire   clkfb;
+   wire   locked;
+   reg 	  locked_r;
+
+   PLL_BASE
+     #(.BANDWIDTH("OPTIMIZED"),
+       .CLKFBOUT_MULT(16),
+       .CLKIN_PERIOD(20.0), //50MHz
+       .CLKOUT1_DIVIDE(50), //16MHz
+       .DIVCLK_DIVIDE(1))
+   PLL_BASE_inst
+     (.CLKOUT1(o_clk),
+      .CLKOUT2(),
+      .CLKOUT3(),
+      .CLKOUT4(),
+      .CLKOUT5(),
+      .CLKFBOUT(clkfb),
+      .LOCKED(locked),
+      .CLKIN(i_clk),
+      .RST(1'b0),
+      .CLKFBIN(clkfb));
+
+   always @(posedge o_clk) begin
+      locked_r <= locked;
+      o_rst  <= !locked_r;
+   end
+
+endmodule