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Use Servile as a base for servant
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Olof Kindgren
@@ -13,103 +13,75 @@ module servant
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parameter [0:0] compress = 0;
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parameter [0:0] align = compress;
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`ifdef MDU
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localparam [0:0] with_mdu = 1'b1;
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`else
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localparam [0:0] with_mdu = 1'b0;
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`endif
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localparam aw = $clog2(memsize);
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localparam csr_regs = with_csr*4;
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localparam rf_width = 2;
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localparam rf_l2d = $clog2((32+csr_regs)*32/rf_width);
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wire timer_irq;
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wire [31:0] wb_ibus_adr;
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wire wb_ibus_cyc;
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wire [31:0] wb_ibus_rdt;
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wire wb_ibus_ack;
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wire [31:0] wb_dbus_adr;
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wire [31:0] wb_dbus_dat;
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wire [3:0] wb_dbus_sel;
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wire wb_dbus_we;
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wire wb_dbus_cyc;
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wire [31:0] wb_dbus_rdt;
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wire wb_dbus_ack;
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wire [31:0] wb_dmem_adr;
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wire [31:0] wb_dmem_dat;
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wire [3:0] wb_dmem_sel;
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wire wb_dmem_we;
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wire wb_dmem_cyc;
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wire [31:0] wb_dmem_rdt;
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wire wb_dmem_ack;
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wire [31:0] wb_mem_adr;
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wire [31:0] wb_mem_dat;
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wire [3:0] wb_mem_sel;
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wire wb_mem_we;
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wire wb_mem_cyc;
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wire wb_mem_stb;
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wire [31:0] wb_mem_rdt;
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wire wb_mem_ack;
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wire wb_gpio_dat;
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wire wb_gpio_we;
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wire wb_gpio_cyc;
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wire wb_gpio_stb;
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wire wb_gpio_rdt;
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wire [31:0] wb_timer_dat;
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wire wb_timer_we;
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wire wb_timer_cyc;
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wire wb_timer_stb;
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wire [31:0] wb_timer_rdt;
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wire [31:0] mdu_rs1;
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wire [31:0] mdu_rs2;
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wire [ 2:0] mdu_op;
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wire mdu_valid;
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wire [31:0] mdu_rd;
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wire mdu_ready;
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wire [31:0] wb_ext_adr;
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wire [31:0] wb_ext_dat;
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wire [3:0] wb_ext_sel;
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wire wb_ext_we;
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wire wb_ext_stb;
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wire [31:0] wb_ext_rdt;
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wire wb_ext_ack;
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servant_arbiter arbiter
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(.i_wb_cpu_dbus_adr (wb_dmem_adr),
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.i_wb_cpu_dbus_dat (wb_dmem_dat),
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.i_wb_cpu_dbus_sel (wb_dmem_sel),
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.i_wb_cpu_dbus_we (wb_dmem_we ),
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.i_wb_cpu_dbus_cyc (wb_dmem_cyc),
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.o_wb_cpu_dbus_rdt (wb_dmem_rdt),
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.o_wb_cpu_dbus_ack (wb_dmem_ack),
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wire [rf_l2d-1:0] rf_waddr;
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wire [rf_width-1:0] rf_wdata;
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wire rf_wen;
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wire [rf_l2d-1:0] rf_raddr;
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wire rf_ren;
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wire [rf_width-1:0] rf_rdata;
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.i_wb_cpu_ibus_adr (wb_ibus_adr),
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.i_wb_cpu_ibus_cyc (wb_ibus_cyc),
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.o_wb_cpu_ibus_rdt (wb_ibus_rdt),
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.o_wb_cpu_ibus_ack (wb_ibus_ack),
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.o_wb_cpu_adr (wb_mem_adr),
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.o_wb_cpu_dat (wb_mem_dat),
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.o_wb_cpu_sel (wb_mem_sel),
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.o_wb_cpu_we (wb_mem_we ),
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.o_wb_cpu_cyc (wb_mem_cyc),
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.i_wb_cpu_rdt (wb_mem_rdt),
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.i_wb_cpu_ack (wb_mem_ack));
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servant_mux #(sim) servant_mux
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servant_mux servant_mux
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(
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.i_clk (wb_clk),
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.i_rst (wb_rst & (reset_strategy != "NONE")),
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.i_wb_cpu_adr (wb_dbus_adr),
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.i_wb_cpu_dat (wb_dbus_dat),
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.i_wb_cpu_sel (wb_dbus_sel),
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.i_wb_cpu_we (wb_dbus_we),
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.i_wb_cpu_cyc (wb_dbus_cyc),
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.o_wb_cpu_rdt (wb_dbus_rdt),
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.o_wb_cpu_ack (wb_dbus_ack),
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.o_wb_mem_adr (wb_dmem_adr),
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.o_wb_mem_dat (wb_dmem_dat),
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.o_wb_mem_sel (wb_dmem_sel),
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.o_wb_mem_we (wb_dmem_we),
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.o_wb_mem_cyc (wb_dmem_cyc),
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.i_wb_mem_rdt (wb_dmem_rdt),
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.i_wb_cpu_adr (wb_ext_adr),
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.i_wb_cpu_dat (wb_ext_dat),
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.i_wb_cpu_sel (wb_ext_sel),
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.i_wb_cpu_we (wb_ext_we),
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.i_wb_cpu_cyc (wb_ext_stb),
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.o_wb_cpu_rdt (wb_ext_rdt),
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.o_wb_cpu_ack (wb_ext_ack),
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.o_wb_gpio_dat (wb_gpio_dat),
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.o_wb_gpio_we (wb_gpio_we),
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.o_wb_gpio_cyc (wb_gpio_cyc),
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.o_wb_gpio_cyc (wb_gpio_stb),
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.i_wb_gpio_rdt (wb_gpio_rdt),
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.o_wb_timer_dat (wb_timer_dat),
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.o_wb_timer_we (wb_timer_we),
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.o_wb_timer_cyc (wb_timer_cyc),
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.o_wb_timer_cyc (wb_timer_stb),
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.i_wb_timer_rdt (wb_timer_rdt));
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servant_ram
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@@ -121,114 +93,78 @@ module servant
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.i_wb_clk (wb_clk),
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.i_wb_rst (wb_rst),
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.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
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.i_wb_cyc (wb_mem_cyc),
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.i_wb_cyc (wb_mem_stb),
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.i_wb_we (wb_mem_we) ,
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.i_wb_sel (wb_mem_sel),
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.i_wb_dat (wb_mem_dat),
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.o_wb_rdt (wb_mem_rdt),
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.o_wb_ack (wb_mem_ack));
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generate
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if (|with_csr) begin
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servant_timer
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#(.RESET_STRATEGY (reset_strategy),
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.WIDTH (32))
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timer
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(.i_clk (wb_clk),
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.i_rst (wb_rst),
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.o_irq (timer_irq),
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.i_wb_cyc (wb_timer_cyc),
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.i_wb_we (wb_timer_we) ,
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.i_wb_dat (wb_timer_dat),
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.o_wb_dat (wb_timer_rdt));
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end else begin
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assign wb_timer_rdt = 32'd0;
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assign timer_irq = 1'b0;
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end
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endgenerate
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servant_timer
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#(.RESET_STRATEGY (reset_strategy),
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.WIDTH (32))
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timer
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(.i_clk (wb_clk),
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.i_rst (wb_rst),
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.o_irq (timer_irq),
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.i_wb_cyc (wb_timer_stb),
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.i_wb_we (wb_timer_we) ,
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.i_wb_dat (wb_timer_dat),
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.o_wb_dat (wb_timer_rdt));
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servant_gpio gpio
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(.i_wb_clk (wb_clk),
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.i_wb_dat (wb_gpio_dat),
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.i_wb_we (wb_gpio_we),
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.i_wb_cyc (wb_gpio_cyc),
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.i_wb_cyc (wb_gpio_stb),
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.o_wb_rdt (wb_gpio_rdt),
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.o_gpio (q));
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serv_rf_top
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#(.RESET_PC (32'h0000_0000),
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.RESET_STRATEGY (reset_strategy),
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`ifdef MDU
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.MDU(1),
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`endif
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.WITH_CSR (with_csr),
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.COMPRESSED(compress),
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.ALIGN(align))
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serv_rf_ram
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#(.width (rf_width),
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.csr_regs (csr_regs))
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rf_ram
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(.i_clk (wb_clk),
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.i_waddr (rf_waddr),
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.i_wdata (rf_wdata),
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.i_wen (rf_wen),
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.i_raddr (rf_raddr),
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.i_ren (rf_ren),
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.o_rdata (rf_rdata));
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servile
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#(.rf_width (rf_width),
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.sim (sim[0]),
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.with_c (compress[0]),
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.with_csr (with_csr[0]),
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.with_mdu (with_mdu))
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cpu
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(
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.clk (wb_clk),
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.i_rst (wb_rst),
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.i_clk (wb_clk),
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.i_rst (wb_rst),
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.i_timer_irq (timer_irq),
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`ifdef RISCV_FORMAL
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.rvfi_valid (),
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.rvfi_order (),
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.rvfi_insn (),
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.rvfi_trap (),
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.rvfi_halt (),
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.rvfi_intr (),
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.rvfi_mode (),
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.rvfi_ixl (),
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.rvfi_rs1_addr (),
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.rvfi_rs2_addr (),
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.rvfi_rs1_rdata (),
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.rvfi_rs2_rdata (),
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.rvfi_rd_addr (),
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.rvfi_rd_wdata (),
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.rvfi_pc_rdata (),
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.rvfi_pc_wdata (),
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.rvfi_mem_addr (),
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.rvfi_mem_rmask (),
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.rvfi_mem_wmask (),
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.rvfi_mem_rdata (),
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.rvfi_mem_wdata (),
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`endif
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.o_ibus_adr (wb_ibus_adr),
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.o_ibus_cyc (wb_ibus_cyc),
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.i_ibus_rdt (wb_ibus_rdt),
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.i_ibus_ack (wb_ibus_ack),
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.o_wb_mem_adr (wb_mem_adr),
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.o_wb_mem_dat (wb_mem_dat),
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.o_wb_mem_sel (wb_mem_sel),
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.o_wb_mem_we (wb_mem_we),
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.o_wb_mem_stb (wb_mem_stb),
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.i_wb_mem_rdt (wb_mem_rdt),
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.i_wb_mem_ack (wb_mem_ack),
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.o_dbus_adr (wb_dbus_adr),
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.o_dbus_dat (wb_dbus_dat),
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.o_dbus_sel (wb_dbus_sel),
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.o_dbus_we (wb_dbus_we),
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.o_dbus_cyc (wb_dbus_cyc),
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.i_dbus_rdt (wb_dbus_rdt),
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.i_dbus_ack (wb_dbus_ack),
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.o_wb_ext_adr (wb_ext_adr),
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.o_wb_ext_dat (wb_ext_dat),
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.o_wb_ext_sel (wb_ext_sel),
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.o_wb_ext_we (wb_ext_we),
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.o_wb_ext_stb (wb_ext_stb),
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.i_wb_ext_rdt (wb_ext_rdt),
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.i_wb_ext_ack (wb_ext_ack),
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//Extension
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.o_ext_rs1 (mdu_rs1),
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.o_ext_rs2 (mdu_rs2),
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.o_ext_funct3 (mdu_op),
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.i_ext_rd (mdu_rd),
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.i_ext_ready (mdu_ready),
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//MDU
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.o_mdu_valid (mdu_valid));
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`ifdef MDU
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mdu_top mdu_serv
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(
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.i_clk(wb_clk),
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.i_rst(wb_rst),
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.i_mdu_rs1(mdu_rs1),
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.i_mdu_rs2(mdu_rs2),
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.i_mdu_op(mdu_op),
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.i_mdu_valid(mdu_valid),
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.o_mdu_ready(mdu_ready),
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.o_mdu_rd(mdu_rd));
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`else
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assign mdu_ready = 1'b0;
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assign mdu_rd = 32'b0;
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`endif
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.o_rf_waddr (rf_waddr),
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.o_rf_wdata (rf_wdata),
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.o_rf_wen (rf_wen),
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.o_rf_raddr (rf_raddr),
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.o_rf_ren (rf_ren),
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.i_rf_rdata (rf_rdata));
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endmodule
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