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Use Servile as a base for servant

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Olof Kindgren
2024-01-29 22:28:05 +01:00
parent 8d91e2d288
commit 970c6fddca
6 changed files with 98 additions and 240 deletions
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44
servant/servant_mux.v
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@@ -16,13 +16,6 @@ module servant_mux
output wire [31:0] o_wb_cpu_rdt,
output reg o_wb_cpu_ack,
output wire [31:0] o_wb_mem_adr,
output wire [31:0] o_wb_mem_dat,
output wire [3:0] o_wb_mem_sel,
output wire o_wb_mem_we,
output wire o_wb_mem_cyc,
input wire [31:0] i_wb_mem_rdt,
output wire o_wb_gpio_dat,
output wire o_wb_gpio_we,
output wire o_wb_gpio_cyc,
@@ -37,8 +30,8 @@ module servant_mux
wire [1:0] s = i_wb_cpu_adr[31:30];
assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt :
s[0] ? {31'd0,i_wb_gpio_rdt} : i_wb_mem_rdt;
assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt : {31'd0,i_wb_gpio_rdt};
always @(posedge i_clk) begin
o_wb_cpu_ack <= 1'b0;
if (i_wb_cpu_cyc & !o_wb_cpu_ack)
@@ -47,43 +40,12 @@ module servant_mux
o_wb_cpu_ack <= 1'b0;
end
assign o_wb_mem_adr = i_wb_cpu_adr;
assign o_wb_mem_dat = i_wb_cpu_dat;
assign o_wb_mem_sel = i_wb_cpu_sel;
assign o_wb_mem_we = i_wb_cpu_we;
assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);
assign o_wb_gpio_dat = i_wb_cpu_dat[0];
assign o_wb_gpio_we = i_wb_cpu_we;
assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);
assign o_wb_gpio_cyc = i_wb_cpu_cyc & !s[1];
assign o_wb_timer_dat = i_wb_cpu_dat;
assign o_wb_timer_we = i_wb_cpu_we;
assign o_wb_timer_cyc = i_wb_cpu_cyc & s[1];
generate
if (sim) begin
wire sig_en = (i_wb_cpu_adr[31:28] == 4'h8) & i_wb_cpu_cyc & o_wb_cpu_ack;
wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
reg [1023:0] signature_file;
integer f = 0;
initial
/* verilator lint_off WIDTH */
if ($value$plusargs("signature=%s", signature_file)) begin
$display("Writing signature to %0s", signature_file);
f = $fopen(signature_file, "w");
end
/* verilator lint_on WIDTH */
always @(posedge i_clk)
if (sig_en & (f != 0))
$fwrite(f, "%c", i_wb_cpu_dat[7:0]);
else if(halt_en) begin
$display("Test complete");
$finish;
end
end
endgenerate
endmodule