diff --git a/rtl/serv_bufreg.v b/rtl/serv_bufreg.v
index d0d8685..e9358fa 100644
--- a/rtl/serv_bufreg.v
+++ b/rtl/serv_bufreg.v
@@ -12,7 +12,7 @@ module serv_bufreg
    input wire 	      i_imm_en,
    input wire 	      i_clr_lsb,
    output reg [1:0]   o_lsb,
-   output wire [31:0] o_reg,
+   output wire [31:0] o_dbus_adr,
    output wire 	      o_q);
 
    wire 	      c, q;
@@ -37,6 +37,6 @@ module serv_bufreg
    end
 
    assign o_q = data[0];
-   assign o_reg = data;
+   assign o_dbus_adr = {data[31:2], 2'b00};
 
 endmodule
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index 1a13e3f..0463568 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -142,7 +142,6 @@ module serv_top
    wire 	 pending_irq;
 
    wire [1:0]   lsb;
-   wire [31:0]  bufreg_out;
 
    serv_state
      #(.WITH_CSR (WITH_CSR))
@@ -244,8 +243,6 @@ module serv_top
       .o_rd_csr_en        (rd_csr_en),
       .o_rd_alu_en        (rd_alu_en));
 
-   assign o_dbus_adr = {bufreg_out[31:2], 2'b00};
-
    serv_bufreg bufreg
      (
       .i_clk    (clk),
@@ -260,7 +257,7 @@ module serv_top
       .i_imm_en (bufreg_imm_en),
       .i_clr_lsb (bufreg_clr_lsb),
       .o_lsb    (lsb),
-      .o_reg    (bufreg_out),
+      .o_dbus_adr (o_dbus_adr),
       .o_q      (bufreg_q));
 
    serv_ctrl