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Code Issues Releases Wiki Activity

Use ring buffer for counter LSBs

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This commit is contained in:
Olof Kindgren 2019-01-15 07:55:07 +01:00
parent 215da65e82
commit 9a97c535bd
4 changed files with 19 additions and 19 deletions
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7
rtl/serv_csr.v
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@ -3,6 +3,7 @@ module serv_csr
(
input wire i_clk,
input wire [4:0] i_cnt,
input wire [3:0] i_cnt_r,
input wire i_mtip,
output wire o_timer_irq_en,
input wire i_mstatus_en,
@ -66,13 +67,13 @@ module serv_csr
assign o_timer_irq_en = mstatus_mie & mie_mtie;
always @(posedge i_clk) begin
if (i_mstatus_en & (i_cnt == 3))
if (i_mstatus_en & (i_cnt[4:2] == 3'd0) & i_cnt_r[3])
mstatus_mie <= csr_in;
if (i_mie_en & (i_cnt == 7))
if (i_mie_en & (i_cnt[4:2] == 3'd1) & i_cnt_r[3])
mie_mtie <= csr_in;
mstatus <= (i_cnt == 2) ? mstatus_mie : 1'b0;
mstatus <= (i_cnt[4:2] == 0) & i_cnt_r[2] & mstatus_mie;
if (i_trap) begin
mcause[31] <= i_mtip & o_timer_irq_en;

20
rtl/serv_ctrl.v
View File

@ -5,6 +5,8 @@ module serv_ctrl
input wire i_rst,
input wire i_en,
input wire i_pc_en,
input wire [4:0] i_cnt,
input wire [3:0] i_cnt_r,
input wire i_cnt_done,
input wire i_jump,
input wire i_offset,
@ -24,11 +26,7 @@ module serv_ctrl
parameter RESET_PC = 32'd8;
reg en_r;
reg en_2r;
reg en_pc_r;
reg en_pc_2r;
reg en_pc_3r;
wire pc_plus_4;
wire pc_plus_offset;
@ -41,7 +39,7 @@ module serv_ctrl
wire offset_a;
assign plus_4 = en_pc_2r & !en_pc_3r;
assign plus_4 = i_cnt_r[2] & (i_cnt[4:2] == 3'd0);
assign o_ibus_adr[0] = pc;
assign o_bad_pc = pc_plus_offset_aligned;
@ -81,7 +79,7 @@ module serv_ctrl
.rst (i_rst),
.a (offset_a),
.b (i_offset),
.clr (!i_en | (i_cnt_done & !i_pc_en)),
.clr (!i_en | i_cnt_done),
.q (pc_plus_offset),
.o_v ());
@ -89,24 +87,16 @@ module serv_ctrl
always @(posedge clk) begin
en_r <= i_en;
en_2r <= en_r;
en_pc_r <= i_pc_en;
en_pc_2r <= en_pc_r;
en_pc_3r <= en_pc_2r;
if (en_r & !en_2r)
if ((i_cnt[4:2] == 3'd0) & i_cnt_r[1])
o_misalign <= pc_plus_offset;
if (en_pc_r & !i_pc_en)
o_ibus_cyc <= 1'b1;
else if (o_ibus_cyc & i_ibus_ack)
o_ibus_cyc <= 1'b0;
if (i_rst) begin
en_r <= 1'b0;
en_2r <= 1'b0;
en_pc_r <= 1'b1;
en_pc_2r <= 1'b0;
en_pc_3r <= 1'b0;
o_ibus_cyc <= 1'b0;
end
end

6
rtl/serv_decode.v
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@ -9,6 +9,7 @@ module serv_decode
input wire i_wb_en,
input wire i_rf_ready,
output wire [4:0] o_cnt,
output reg [3:0] o_cnt_r,
output wire o_cnt_done,
output wire o_ctrl_en,
output wire o_ctrl_pc_en,
@ -292,7 +293,7 @@ module serv_decode
if (i_mtip & !mtip_r & i_timer_irq_en)
pending_irq <= 1'b1;
cnt_done <= cnt == 30;
cnt_done <= (cnt[4:2] == 3'b111) & o_cnt_r[2];
case (state)
IDLE : begin
@ -325,6 +326,8 @@ module serv_decode
endcase
cnt <= cnt + {4'd0,cnt_en};
if (cnt_en)
o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]};
if (i_rst) begin
state <= IDLE;
@ -332,6 +335,7 @@ module serv_decode
pending_irq <= 1'b0;
stage_one_done <= 1'b0;
o_ctrl_jump <= 1'b0;
o_cnt_r <= 4'b0001;
end
end
endmodule

5
rtl/serv_top.v
View File

@ -71,6 +71,7 @@ module serv_top
wire trap;
wire [4:0] cnt;
wire [3:0] cnt_r;
wire cnt_done;
wire [2:0] funct3;
@ -137,6 +138,7 @@ module serv_top
.i_wb_en (o_ibus_cyc & i_ibus_ack),
.i_rf_ready (rf_ready),
.o_cnt (cnt),
.o_cnt_r (cnt_r),
.o_cnt_done (cnt_done),
.o_ctrl_en (ctrl_en),
.o_ctrl_pc_en (ctrl_pc_en),
@ -195,6 +197,8 @@ module serv_top
.i_rst (i_rst),
.i_en (ctrl_en),
.i_pc_en (ctrl_pc_en),
.i_cnt (cnt),
.i_cnt_r (cnt_r),
.i_cnt_done (cnt_done),
.i_jump (jump),
.i_offset (imm),
@ -283,6 +287,7 @@ module serv_top
(
.i_clk (clk),
.i_cnt (cnt),
.i_cnt_r (cnt_r),
.i_mtip (i_timer_irq),
.o_timer_irq_en ( timer_irq_en),
.i_mstatus_en (csr_mstatus_en),