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Use custom interconnect. Runs on hw

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Olof Kindgren
2018-11-21 12:55:44 +01:00
parent 6e034361d4
commit 9df2a0060b
17 changed files with 2407 additions and 261 deletions
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37
bench/serv_arbiter.v Normal file
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@@ -0,0 +1,37 @@
module serv_arbiter
(
input i_ibus_active,
input [31:0] i_wb_cpu_dbus_adr,
input [31:0] i_wb_cpu_dbus_dat,
input [3:0] i_wb_cpu_dbus_sel,
input i_wb_cpu_dbus_we,
input i_wb_cpu_dbus_cyc,
output [31:0] o_wb_cpu_dbus_rdt,
output o_wb_cpu_dbus_ack,
input [31:0] i_wb_cpu_ibus_adr,
input i_wb_cpu_ibus_cyc,
output [31:0] o_wb_cpu_ibus_rdt,
output o_wb_cpu_ibus_ack,
output [31:0] o_wb_cpu_adr,
output [31:0] o_wb_cpu_dat,
output [3:0] o_wb_cpu_sel,
output o_wb_cpu_we,
output o_wb_cpu_cyc,
input [31:0] i_wb_cpu_rdt,
input i_wb_cpu_ack);
assign o_wb_cpu_dbus_rdt = i_wb_cpu_rdt;
assign o_wb_cpu_dbus_ack = i_wb_cpu_ack & !i_ibus_active;
assign o_wb_cpu_ibus_rdt = i_wb_cpu_rdt;
assign o_wb_cpu_ibus_ack = i_wb_cpu_ack & i_ibus_active;
assign o_wb_cpu_adr = i_ibus_active ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr;
assign o_wb_cpu_dat = i_wb_cpu_dbus_dat;
assign o_wb_cpu_sel = i_wb_cpu_dbus_sel;
assign o_wb_cpu_we = i_wb_cpu_dbus_we & !i_ibus_active;
assign o_wb_cpu_cyc = i_ibus_active ? i_wb_cpu_ibus_cyc : i_wb_cpu_dbus_cyc;
endmodule

83
bench/serv_mux.v Normal file
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@@ -0,0 +1,83 @@
/*
mem = 00
gpio = 01
timer = 10
testcon = 11
*/
module serv_mux
(
input i_clk,
input i_rst,
input [31:0] i_wb_cpu_adr,
input [31:0] i_wb_cpu_dat,
input [3:0] i_wb_cpu_sel,
input i_wb_cpu_we,
input i_wb_cpu_cyc,
output [31:0] o_wb_cpu_rdt,
output reg o_wb_cpu_ack,
output [31:0] o_wb_mem_adr,
output [31:0] o_wb_mem_dat,
output [3:0] o_wb_mem_sel,
output o_wb_mem_we,
output o_wb_mem_cyc,
input [31:0] i_wb_mem_rdt,
output o_wb_gpio_dat,
output o_wb_gpio_cyc,
output [31:0] o_wb_timer_dat,
output o_wb_timer_we,
output o_wb_timer_cyc,
input [31:0] i_wb_timer_rdt);
parameter sim = 0;
wire [1:0] s = i_wb_cpu_adr[31:30];
assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt : i_wb_mem_rdt;
always @(posedge i_clk) begin
o_wb_cpu_ack <= 1'b0;
if (i_wb_cpu_cyc & !o_wb_cpu_ack)
o_wb_cpu_ack <= 1'b1;
if (i_rst)
o_wb_cpu_ack <= 1'b0;
end
assign o_wb_mem_adr = i_wb_cpu_adr;
assign o_wb_mem_dat = i_wb_cpu_dat;
assign o_wb_mem_sel = i_wb_cpu_sel;
assign o_wb_mem_we = i_wb_cpu_we;
assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);
assign o_wb_gpio_dat = i_wb_cpu_dat[0];
assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);
assign o_wb_timer_dat = i_wb_cpu_dat;
assign o_wb_timer_we = i_wb_cpu_we;
assign o_wb_timer_cyc = i_wb_cpu_cyc & s[1];
generate
if (sim) begin
wire sig_en = (i_wb_cpu_adr[31:28] == 8'h8) & i_wb_cpu_cyc & o_wb_cpu_ack;
wire halt_en = (i_wb_cpu_adr[31:28] == 8'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
reg [1023:0] signature_file;
integer f = 0;
initial
if ($value$plusargs("signature=%s", signature_file)) begin
$display("Writing signature to %0s", signature_file);
f = $fopen(signature_file, "w");
end
always @(posedge i_clk)
if (sig_en & (f != 0))
$fwrite(f, "%c", i_wb_cpu_dat[7:0]);
else if(halt_en) begin
$display("Test complete");
$finish;
end
end
endgenerate
endmodule

202
bench/serv_wrapper.v
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@@ -4,8 +4,8 @@ module serv_wrapper
input wire wb_clk,
output wire q);
// parameter memfile = "hellomin.hex";
parameter memfile = "bitbang.hex";
parameter memfile = "helloservice4000.hex";
// parameter memfile = "bitbang.hex";
reg [4:0] rst_reg = 5'b11111;
@@ -16,7 +16,96 @@ module serv_wrapper
wire timer_irq;
`include "wb_intercon.vh"
wire [31:0] wb_cpu_ibus_adr;
wire wb_cpu_ibus_cyc;
wire [31:0] wb_cpu_ibus_rdt;
wire wb_cpu_ibus_ack;
wire [31:0] wb_cpu_dbus_adr;
wire [31:0] wb_cpu_dbus_dat;
wire [3:0] wb_cpu_dbus_sel;
wire wb_cpu_dbus_we;
wire wb_cpu_dbus_cyc;
wire [31:0] wb_cpu_dbus_rdt;
wire wb_cpu_dbus_ack;
wire [31:0] wb_cpu_adr;
wire [31:0] wb_cpu_dat;
wire [3:0] wb_cpu_sel;
wire wb_cpu_we;
wire wb_cpu_cyc;
wire [31:0] wb_cpu_rdt;
wire wb_cpu_ack;
wire [31:0] wb_mem_adr;
wire [31:0] wb_mem_dat;
wire [3:0] wb_mem_sel;
wire wb_mem_we;
wire wb_mem_cyc;
wire [31:0] wb_mem_rdt;
wire wb_gpio_dat;
wire wb_gpio_cyc;
wire [31:0] wb_timer_dat;
wire wb_timer_we;
wire wb_timer_cyc;
wire [31:0] wb_timer_rdt;
serv_arbiter serv_arbiter
(
.i_ibus_active (wb_cpu_ibus_cyc),
.i_wb_cpu_dbus_adr (wb_cpu_dbus_adr),
.i_wb_cpu_dbus_dat (wb_cpu_dbus_dat),
.i_wb_cpu_dbus_sel (wb_cpu_dbus_sel),
.i_wb_cpu_dbus_we (wb_cpu_dbus_we ),
.i_wb_cpu_dbus_cyc (wb_cpu_dbus_cyc),
.o_wb_cpu_dbus_rdt (wb_cpu_dbus_rdt),
.o_wb_cpu_dbus_ack (wb_cpu_dbus_ack),
.i_wb_cpu_ibus_adr (wb_cpu_ibus_adr),
.i_wb_cpu_ibus_cyc (wb_cpu_ibus_cyc),
.o_wb_cpu_ibus_rdt (wb_cpu_ibus_rdt),
.o_wb_cpu_ibus_ack (wb_cpu_ibus_ack),
.o_wb_cpu_adr (wb_cpu_adr),
.o_wb_cpu_dat (wb_cpu_dat),
.o_wb_cpu_sel (wb_cpu_sel),
.o_wb_cpu_we (wb_cpu_we ),
.o_wb_cpu_cyc (wb_cpu_cyc),
.i_wb_cpu_rdt (wb_cpu_rdt),
.i_wb_cpu_ack (wb_cpu_ack));
`ifdef VERILATOR
parameter sim = 1;
`else
parameter sim = 0;
`endif
serv_mux #(sim) serv_mux
(
.i_clk (wb_clk),
.i_rst (wb_rst),
.i_wb_cpu_adr (wb_cpu_adr),
.i_wb_cpu_dat (wb_cpu_dat),
.i_wb_cpu_sel (wb_cpu_sel),
.i_wb_cpu_we (wb_cpu_we),
.i_wb_cpu_cyc (wb_cpu_cyc),
.o_wb_cpu_rdt (wb_cpu_rdt),
.o_wb_cpu_ack (wb_cpu_ack),
.o_wb_mem_adr (wb_mem_adr),
.o_wb_mem_dat (wb_mem_dat),
.o_wb_mem_sel (wb_mem_sel),
.o_wb_mem_we (wb_mem_we),
.o_wb_mem_cyc (wb_mem_cyc),
.i_wb_mem_rdt (wb_mem_rdt),
.o_wb_gpio_dat (wb_gpio_dat),
.o_wb_gpio_cyc (wb_gpio_cyc),
.o_wb_timer_dat (wb_timer_dat),
.o_wb_timer_we (wb_timer_we),
.o_wb_timer_cyc (wb_timer_cyc),
.i_wb_timer_rdt (wb_timer_rdt));
localparam MEMORY_SIZE = 2048*4;
@@ -41,99 +130,52 @@ module serv_wrapper
(// Wishbone interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_m2s_mem_adr[$clog2(MEMORY_SIZE)-1:0]),
.wb_stb_i (wb_m2s_mem_stb),
.wb_cyc_i (wb_m2s_mem_cyc),
.wb_cti_i (wb_m2s_mem_cti),
.wb_bte_i (wb_m2s_mem_bte),
.wb_we_i (wb_m2s_mem_we) ,
.wb_sel_i (wb_m2s_mem_sel),
.wb_dat_i (wb_m2s_mem_dat),
.wb_dat_o (wb_s2m_mem_dat),
.wb_ack_o (wb_s2m_mem_ack),
.wb_adr_i (wb_mem_adr[$clog2(MEMORY_SIZE)-1:0]),
.wb_stb_i (1'b1),
.wb_cyc_i (wb_mem_cyc),
.wb_cti_i (3'b000),
.wb_bte_i (2'b00),
.wb_we_i (wb_mem_we) ,
.wb_sel_i (wb_mem_sel),
.wb_dat_i (wb_mem_dat),
.wb_dat_o (wb_mem_rdt),
.wb_ack_o (),
.wb_err_o ());
testprint testprint
(
.i_wb_clk (wb_clk),
.i_wb_dat (wb_m2s_testprint_dat),
.i_wb_we (wb_m2s_testprint_we),
.i_wb_cyc (wb_m2s_testprint_cyc),
.i_wb_stb (wb_m2s_testprint_stb),
.o_wb_ack (wb_s2m_testprint_ack));
assign wb_s2m_testprint_dat = 32'h0;
testhalt testhalt
(
.i_wb_clk (wb_clk),
.i_wb_dat (wb_m2s_testhalt_dat),
.i_wb_we (wb_m2s_testhalt_we),
.i_wb_cyc (wb_m2s_testhalt_cyc),
.i_wb_stb (wb_m2s_testhalt_stb),
.o_wb_ack (wb_s2m_testhalt_ack));
assign wb_s2m_testhalt_dat = 32'h0;
riscv_timer riscv_timer
(.i_clk (wb_clk),
.o_irq (timer_irq),
.i_wb_adr (wb_m2s_timer_adr),
.i_wb_stb (wb_m2s_timer_stb),
.i_wb_cyc (wb_m2s_timer_cyc),
.i_wb_we (wb_m2s_timer_we) ,
.i_wb_sel (wb_m2s_timer_sel),
.i_wb_dat (wb_m2s_timer_dat),
.o_wb_dat (wb_s2m_timer_dat),
.o_wb_ack (wb_s2m_timer_ack));
.i_wb_cyc (wb_timer_cyc),
.i_wb_we (wb_timer_we) ,
.i_wb_dat (wb_timer_dat),
.o_wb_dat (wb_timer_rdt));
wb_gpio gpio
(.i_wb_clk (wb_clk),
.i_wb_rst (wb_rst),
.i_wb_dat (wb_m2s_gpio_dat[0]),
.i_wb_cyc (wb_m2s_gpio_cyc),
.o_wb_ack (wb_s2m_gpio_ack),
.i_wb_dat (wb_gpio_dat),
.i_wb_cyc (wb_gpio_cyc),
.o_gpio (q));
reg canary;
always @(posedge wb_clk)
if (wb_rst)
canary <= 1'b0;
/*else if (wb_m2s_cpu_ibus_cyc &
wb_s2m_cpu_ibus_ack &
(wb_m2s_cpu_ibus_adr == 32'h00000020))*/
else if (wb_m2s_cpu_dbus_cyc & wb_s2m_cpu_dbus_ack)
canary <= ~canary;
// assign q = canary;
assign wb_s2m_gpio_dat = 32'h0;
serv_top
#(.RESET_PC (32'h0000_0000))
cpu
(
.clk (wb_clk),
.i_rst (wb_rst),
.o_ibus_adr (wb_m2s_cpu_ibus_adr),
.o_ibus_cyc (wb_m2s_cpu_ibus_cyc),
.o_ibus_stb (wb_m2s_cpu_ibus_stb),
.i_ibus_rdt (wb_s2m_cpu_ibus_dat),
.i_ibus_ack (wb_s2m_cpu_ibus_ack),
.o_dbus_adr (wb_m2s_cpu_dbus_adr),
.o_dbus_dat (wb_m2s_cpu_dbus_dat),
.o_dbus_sel (wb_m2s_cpu_dbus_sel),
.o_dbus_we (wb_m2s_cpu_dbus_we),
.o_dbus_cyc (wb_m2s_cpu_dbus_cyc),
.o_dbus_stb (wb_m2s_cpu_dbus_stb),
.i_dbus_rdt (wb_s2m_cpu_dbus_dat),
.i_dbus_ack (wb_s2m_cpu_dbus_ack));
assign wb_m2s_cpu_ibus_dat = 32'd0;
assign wb_m2s_cpu_ibus_we = 1'b0;
assign wb_m2s_cpu_ibus_sel = 4'b1111;
assign wb_m2s_cpu_ibus_cti = 3'b000;
assign wb_m2s_cpu_ibus_bte = 2'b00;
.o_ibus_adr (wb_cpu_ibus_adr),
.o_ibus_cyc (wb_cpu_ibus_cyc),
.o_ibus_stb (),
.i_ibus_rdt (wb_cpu_ibus_rdt),
.i_ibus_ack (wb_cpu_ibus_ack),
.o_dbus_adr (wb_cpu_dbus_adr),
.o_dbus_dat (wb_cpu_dbus_dat),
.o_dbus_sel (wb_cpu_dbus_sel),
.o_dbus_we (wb_cpu_dbus_we),
.o_dbus_cyc (wb_cpu_dbus_cyc),
.o_dbus_stb (),
.i_dbus_rdt (wb_cpu_dbus_rdt),
.i_dbus_ack (wb_cpu_dbus_ack));
endmodule