Use custom interconnect. Runs on hw

rtl/ser_add.v

@@ -2,18 +2,24 @@
 module ser_add
   (
    input wire  clk,
+   input wire  rst,
    input wire  a,
    input wire  b,
    input wire  clr,
    output wire q,
    output wire o_v);
 
-   reg 	       c_r = 1'b0;
+   reg 	       c_r;
 
-   assign o_v = (a&b | a&c_r | b&c_r);
+   wire axorb = a^b;
 
-   assign q   = a ^ b ^ c_r;
+   assign o_v = (axorb & c_r) | (a&b);
+
+   assign q   = axorb ^ c_r;
    always @(posedge clk)
-     c_r <= !clr & o_v;
+     if (rst)
+       c_r <= 1'b0;
+     else
+       c_r <= !clr & o_v;
 
 endmodule