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Fix typos

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This commit is contained in:
Nazar Kazakov
2024-04-05 12:03:14 +01:00
committed by Olof Kindgren
parent bebc875353
commit a26c2965c0
11 changed files with 32 additions and 32 deletions
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2
rtl/serv_csr.v
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@@ -94,7 +94,7 @@ module serv_csr
During a mstatus CSR access instruction it's assigned when
bit 3 gets updated
These conditions are all mutually exclusibe
These conditions are all mutually exclusive
*/
if ((i_trap & i_cnt_done) | i_mstatus_en & i_cnt3 & i_en | i_mret)
mstatus_mie <= !i_trap & (i_mret ? mstatus_mpie : csr_in[B]);

6
rtl/serv_state.v
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@@ -105,10 +105,10 @@ module serv_state
assign o_rf_rd_en = i_rd_op & !o_init;
/*
bufreg is used during mem. branch and shift operations
bufreg is used during mem, branch, and shift operations
mem : bufreg is used for dbus address. Shift in data during phase 1.
Shift out during phase 2 if there was an misalignment exception.
Shift out during phase 2 if there was a misalignment exception.
branch : Shift in during phase 1. Shift out during phase 2
@@ -127,7 +127,7 @@ module serv_state
//ibus_cyc changes on three conditions.
//1. i_rst is asserted. Together with the async gating above, o_ibus_cyc
// will be asserted as soon as the reset is released. This is how the
// first instruction is fetced
// first instruction is fetched
//2. o_cnt_done and o_ctrl_pc_en are asserted. This means that SERV just
// finished updating the PC, is done with the current instruction and
// o_ibus_cyc gets asserted to fetch a new instruction