Add ulx3s 85k servant target

data/ulx3s.lpf

@@ -0,0 +1,14 @@
+LOCATE COMP "clk" SITE "G2";
+IOBUF  PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk" 25.000 MHZ;
+LOCATE COMP "q" SITE "B2";
+IOBUF  PORT "q" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "btn0" SITE "D6";  # BTN_PWRn (inverted logic)
+IOBUF PORT "btn0" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+LOCATE COMP "wifi_gpio0" SITE "L2";
+IOBUF  PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "uart_txd" SITE "L4"; # FPGA transmits to ftdi
+IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;

servant.core

@@ -57,6 +57,13 @@ filesets:
       - servant/servix.v : {file_type : verilogSource}
       - data/arty_a7_35t.xdc : {file_type : xdc}
 
+  ulx3s:
+    files:
+      - data/ulx3s.lpf : {file_type : LPF}
+      - servant/ecppll.v : {file_type : verilogSource}
+      - servant/servant_ecp5_clock_gen.v : {file_type : verilogSource}
+      - servant/servant_ecp5.v : {file_type : verilogSource}
+
   zcu106:
     files:
       - servant/servus_clock_gen.v : {file_type : verilogSource}
@@ -134,6 +141,18 @@ targets:
       - memsize
     toplevel : servant_tb
 
+  ulx3s_85:
+    default_tool: diamond
+    description : ULX3S 85k version
+    filesets : [mem_files, soc, ulx3s]
+    parameters : [memfile, memsize]
+    tools:
+      diamond:
+        part : LFE5U-85F-6BG381C
+      trellis:
+        nextpnr_options : [--package, CABGA381, --85k]
+    toplevel: servant_ecp5
+
   verilator_tb:
     default_tool: verilator
     filesets : [soc, servant_tb]

servant/ecppll.v

@@ -0,0 +1,38 @@
+module pll(input clki, 
+    output locked,
+    output clko
+);
+wire clkfb;
+wire clkos;
+wire clkop;
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .CLKOP_FPHASE(0),
+        .CLKOP_CPHASE(18),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(38),
+        .CLKFB_DIV(5),
+        .CLKI_DIV(8),
+        .FEEDBK_PATH("INT_OP")
+    ) pll_i (
+        .CLKI(clki),
+        .CLKFB(clkfb),
+        .CLKINTFB(clkfb),
+        .CLKOP(clkop),
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b0),
+        .PHASESTEP(1'b0),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(locked)
+	);
+assign clko = clkop;
+endmodule

servant/servant_ecp5.v

@@ -0,0 +1,33 @@
+`default_nettype none
+module servant_ecp5
+(
+ input wire  clk,
+ input wire btn0,
+ output wire wifi_gpio0,
+ output wire uart_txd,
+ output wire q);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   assign wifi_gpio0 = btn0;
+   assign uart_txd = q;
+
+   servant_ecp5_clock_gen clock_gen
+     (.i_clk (clk),
+      .i_rst (!btn0),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule

servant/servant_ecp5_clock_gen.v

@@ -0,0 +1,25 @@
+`default_nettype none
+module servant_ecp5_clock_gen
+  (
+   input  i_clk,
+   input  i_rst,
+   output o_clk,
+   output o_rst);
+
+   wire   locked;
+
+   reg [1:0] rst_reg;
+   always @(posedge o_clk)
+     if (i_rst)
+       rst_reg <= 2'b11;
+     else
+       rst_reg <= {!locked, rst_reg[1]};
+
+   assign o_rst = rst_reg[0];
+
+   pll pll
+     (.clki   (i_clk),
+      .clko   (o_clk),
+      .locked (locked));
+
+endmodule