From a974320f46ce6638b7ae0c86e4cf563c22384d7c Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 23 Nov 2018 21:26:49 +0100 Subject: [PATCH] Further optimizations --- bench/serv_wrapper.v | 5 +-- cores/wb_ram_1.1/rtl/verilog/wb_ram.v | 21 +-------- rtl/riscv_timer.v | 9 +++- rtl/serv_ctrl.v | 3 -- rtl/serv_decode.v | 64 +++++++++++---------------- rtl/serv_mem_if.v | 6 +-- rtl/serv_top.v | 1 - 7 files changed, 41 insertions(+), 68 deletions(-) diff --git a/bench/serv_wrapper.v b/bench/serv_wrapper.v index bbd0c14..2db2b23 100644 --- a/bench/serv_wrapper.v +++ b/bench/serv_wrapper.v @@ -129,17 +129,16 @@ serv_arbiter serv_arbiter ram (// Wishbone interface .wb_clk_i (wb_clk), - .wb_rst_i (wb_rst), .wb_adr_i (wb_mem_adr[$clog2(MEMORY_SIZE)-1:0]), .wb_cyc_i (wb_mem_cyc), .wb_we_i (wb_mem_we) , .wb_sel_i (wb_mem_sel), .wb_dat_i (wb_mem_dat), - .wb_dat_o (wb_mem_rdt), - .wb_ack_o ()); + .wb_dat_o (wb_mem_rdt)); riscv_timer riscv_timer (.i_clk (wb_clk), + .i_rst (wb_rst), .o_irq (timer_irq), .i_wb_cyc (wb_timer_cyc), .i_wb_we (wb_timer_we) , diff --git a/cores/wb_ram_1.1/rtl/verilog/wb_ram.v b/cores/wb_ram_1.1/rtl/verilog/wb_ram.v index 9bbde3d..d04f2f3 100644 --- a/cores/wb_ram_1.1/rtl/verilog/wb_ram.v +++ b/cores/wb_ram_1.1/rtl/verilog/wb_ram.v @@ -31,7 +31,6 @@ module wb_ram parameter aw = $clog2(depth), parameter memfile = "") (input wire wb_clk_i, - input wire wb_rst_i, input wire [aw-1:0] wb_adr_i, input wire [dw-1:0] wb_dat_i, @@ -39,25 +38,9 @@ module wb_ram input wire wb_we_i, input wire wb_cyc_i, - output reg wb_ack_o = 1'b0, output wire [dw-1:0] wb_dat_o); - wire [31:0] wb_rdt; - reg [31:0] wb_rdt_r; - - always@(posedge wb_clk_i) begin - //Ack generation - wb_ack_o <= wb_cyc_i & !wb_ack_o; - - if (wb_cyc_i) - wb_rdt_r <= wb_rdt; - if (wb_rst_i) - wb_ack_o <= 1'b0; - end - - assign wb_dat_o = (wb_cyc_i) ? wb_rdt : wb_rdt_r; - - wire ram_we = wb_we_i & wb_cyc_i & wb_ack_o; + wire ram_we = wb_we_i & wb_cyc_i; wb_ram_generic #(.depth(depth/4), @@ -68,6 +51,6 @@ module wb_ram .din (wb_dat_i), .waddr(wb_adr_i[aw-1:2]), .raddr (wb_adr_i[aw-1:2]), - .dout (wb_rdt)); + .dout (wb_dat_o)); endmodule diff --git a/rtl/riscv_timer.v b/rtl/riscv_timer.v index 71774bb..f516075 100644 --- a/rtl/riscv_timer.v +++ b/rtl/riscv_timer.v @@ -1,14 +1,15 @@ `default_nettype none module riscv_timer (input wire i_clk, + input wire i_rst, output reg o_irq = 1'b0, input wire [31:0] i_wb_dat, input wire i_wb_we, input wire i_wb_cyc, output wire [31:0] o_wb_dat); - reg [31:0] mtime = 32'd0; - reg [31:0] mtimecmp = 32'd0; + reg [15:0] mtime; + reg [15:0] mtimecmp; assign o_wb_dat = mtime; @@ -17,5 +18,9 @@ module riscv_timer mtimecmp <= i_wb_dat; mtime <= mtime + 32'd1; o_irq <= (mtime >= mtimecmp); + if (i_rst) begin + mtime <= 16'd0; + mtimecmp <= 16'd0; + end end endmodule diff --git a/rtl/serv_ctrl.v b/rtl/serv_ctrl.v index 73c7035..4a18f26 100644 --- a/rtl/serv_ctrl.v +++ b/rtl/serv_ctrl.v @@ -82,7 +82,6 @@ module serv_ctrl reg en_r; reg en_2r; - reg en_3r; reg en_pc_r; reg en_pc_2r; reg en_pc_3r; @@ -90,7 +89,6 @@ module serv_ctrl always @(posedge clk) begin en_r <= i_en; en_2r <= en_r; - en_3r <= en_2r; en_pc_r <= i_pc_en; en_pc_2r <= en_pc_r; en_pc_3r <= en_pc_2r; @@ -104,7 +102,6 @@ module serv_ctrl if (i_rst) begin en_r <= 1'b0; en_2r <= 1'b0; - en_3r <= 1'b0; en_pc_r <= 1'b1; en_pc_2r <= 1'b0; en_pc_3r <= 1'b0; diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v index 316e68b..1ad8a65 100644 --- a/rtl/serv_decode.v +++ b/rtl/serv_decode.v @@ -6,7 +6,6 @@ module serv_decode input wire [31:0] i_wb_rdt, input wire i_wb_en, output wire o_cnt_done, - output wire o_ibus_active, output wire o_ctrl_en, output wire o_ctrl_pc_en, output wire o_ctrl_jump, @@ -72,10 +71,10 @@ module serv_decode OP_JAL = 5'b11011, OP_SYSTEM = 5'b11100; - reg [1:0] state = IDLE; + reg [1:0] state; reg go; - reg [4:0] cnt = 5'd0; + reg [4:0] cnt; wire running; wire mem_op; @@ -84,21 +83,17 @@ module serv_decode wire slt_op; wire branch_op; wire e_op; - wire jump_misaligned; reg imm30; assign o_cnt_done = cnt_done; - assign o_ibus_active = (state == IDLE); - assign mem_op = !opcode[4] & !opcode[2] & !opcode[0]; - assign shift_op = ((opcode == OP_OPIMM) & (o_funct3[1:0] == 2'b01)) | - ((opcode == OP_OP ) & (o_funct3[1:0] == 2'b01)); + wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]); - assign slt_op = (!opcode[4] & opcode[2] & !opcode[0]) & - (o_funct3[2:1] == 2'b01); + assign shift_op = op_or_opimm & (o_funct3[1:0] == 2'b01); + assign slt_op = op_or_opimm & (o_funct3[2:1] == 2'b01); assign branch_op = (opcode[4:2] == 3'b110) & !opcode[0]; @@ -109,21 +104,20 @@ module serv_decode assign o_ctrl_jalr = opcode[4] & (opcode[2:0] == 3'b001); - assign o_ctrl_auipc = (opcode == OP_AUIPC); + assign o_ctrl_auipc = !opcode[3] & opcode[2] & opcode[0]; - assign o_ctrl_mret = (opcode == OP_SYSTEM) & op[21] & !(|o_funct3); + assign o_ctrl_mret = (opcode[4] & opcode[2]) & op[21] & !(|o_funct3); - assign o_rf_rd_en = running & !o_ctrl_trap & - (opcode != OP_STORE) & - !branch_op; + assign o_rf_rd_en = running & (opcode[2] | + (!opcode[2] & opcode[4] & opcode[0]) | + (!opcode[2] & !opcode[3] & !opcode[0])); assign o_rf_rs_en = cnt_en; + assign o_alu_en = cnt_en; + assign o_ctrl_en = cnt_en; - assign o_alu_en = cnt_en; + assign o_ctrl_lui = (opcode[0] & !opcode[4] & opcode[3]); - assign o_ctrl_lui = opcode == OP_LUI; - - assign o_ctrl_en = cnt_en; assign o_alu_init = (state == INIT); @@ -136,12 +130,12 @@ module serv_decode assign o_alu_cmp_neg = branch_op & o_funct3[0]; - assign o_csr_en = ((((opcode == OP_SYSTEM) & (|o_funct3)) | + assign o_csr_en = ((((opcode[4] & opcode[2]) & (|o_funct3)) | o_ctrl_mret) & running) | o_ctrl_trap; wire [3:0] csr_sel = {op[26],op[22:20]}; - always @(o_funct3, op, csr_sel) begin + always @(o_funct3, op, csr_sel, o_rf_rs1_addr, o_ctrl_trap, o_ctrl_mret) begin casez (o_funct3) 3'b00? : o_alu_cmp_sel = ALU_CMP_EQ; 3'b01? : o_alu_cmp_sel = ALU_CMP_LT; @@ -214,10 +208,10 @@ module serv_decode assign o_mem_init = mem_op & (state == INIT); assign o_mem_bytecnt = cnt[4:3]; - wire jal_misalign = op[21] & (opcode == OP_JAL); + wire jal_misalign = op[21] & opcode[1] & opcode[4]; reg [4:0] opcode; - reg [31:0] op; + reg [30:7] op; reg signbit; reg [8:0] imm19_12_20; @@ -234,7 +228,7 @@ module serv_decode o_funct3 <= i_wb_rdt[14:12]; imm30 <= i_wb_rdt[30]; opcode <= i_wb_rdt[6:2]; - op <= i_wb_rdt; + op <= i_wb_rdt[30:7]; signbit <= i_wb_rdt[31]; end if (cnt_done | go | i_mem_dbus_ack) begin @@ -265,7 +259,7 @@ module serv_decode wire m3 = opcode[4]; - wire gate1 = (cnt == 0) & ((opcode == OP_BRANCH) | (opcode == OP_JAL)); + wire gate1 = (cnt == 0) & ((opcode == OP_BRANCH) | (opcode[1] & opcode[4])); wire gate12 = (cnt < 12) & utype; assign o_imm = (!(gate1 | gate12) & (cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0])); @@ -295,25 +289,21 @@ module serv_decode always @(i_mem_misalign, o_mem_cmd, e_op, op) begin o_csr_mcause[3:0] = 4'd0; - if (i_mem_misalign & !o_mem_cmd) - o_csr_mcause[3:0] = 4'd4; - if (i_mem_misalign & o_mem_cmd) - o_csr_mcause[3:0] = 4'd6; - if (e_op & !op[20]) - o_csr_mcause[3:0] = 4'd11; - if (e_op & op[20]) - o_csr_mcause[3:0] = 4'd3; + if (i_mem_misalign) + o_csr_mcause[3:0] = {2'b01, o_mem_cmd, 1'b0}; + if (e_op) + o_csr_mcause = {!op[20],3'b011}; end + wire two_stage_op = + slt_op | (opcode[4:2] == 3'b110) | (opcode[2:1] == 2'b00) | + shift_op; always @(posedge clk) begin - state <= state; case (state) IDLE : begin if (go) begin state <= RUN; - if (branch_op | - slt_op | (opcode == OP_JAL) | (opcode == OP_JALR) | - mem_op | shift_op) + if (two_stage_op) state <= INIT; if (e_op) state <= TRAP; diff --git a/rtl/serv_mem_if.v b/rtl/serv_mem_if.v index 41539b6..279b4a1 100644 --- a/rtl/serv_mem_if.v +++ b/rtl/serv_mem_if.v @@ -77,9 +77,9 @@ module serv_mem_if wire upper_half = bytepos[1]; - wire [3:0] o_wb_sel = (is_word ? 4'b1111 : - is_half ? {{2{upper_half}}, ~{2{upper_half}}} : - 4'd1 << bytepos); + assign o_wb_sel = (is_word ? 4'b1111 : + is_half ? {{2{upper_half}}, ~{2{upper_half}}} : + 4'd1 << bytepos); /* assign o_wb_sel[3] = is_word | (is_half & bytepos[1]) | (bytepos == 2'b11); assign o_wb_sel[2] = (bytepos == 2'b10) | is_word; diff --git a/rtl/serv_top.v b/rtl/serv_top.v index fcff494..e11d0cd 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -122,7 +122,6 @@ module serv_top .i_wb_rdt (i_ibus_rdt), .i_wb_en (o_ibus_cyc & i_ibus_ack), .o_cnt_done (cnt_done), - .o_ibus_active (), .o_ctrl_en (ctrl_en), .o_ctrl_pc_en (ctrl_pc_en), .o_ctrl_jump (jump),