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Remove doc for removed modules
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@@ -170,16 +170,6 @@ serv_state keeps track of the state for the core and contains all dynamic contro
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New instructions are fetched by asserting o_ibus_cyc until there is a response on i_ibus_ack. Instruction fetches occur when the reset signal is deasserted, which is what gets SERV started, or when the PC has finished updating its value.
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shift_reg
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^^^^^^^^^
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shift_reg is a shift register implementation used in various places in SERV
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serv_shift
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^^^^^^^^^^
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serv_shift lives inside the ALU and contains the control logic for shift operations
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Instruction life cycle
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----------------------
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