Port Zephyr support to 2.4 and update instructions

zephyr/soc/riscv/servant/CMakeLists.txt

@@ -0,0 +1,7 @@
+# Copyright (c) 2020 Olof Kindgren <olof.kindgren@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+    soc_irq.S
+    vector.S
+    irq.c)

zephyr/soc/riscv/servant/Kconfig.defconfig

@@ -0,0 +1,26 @@
+# Copyright (c) 2020 Olof Kindgren <olof.kindgren@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RISCV32_SERVANT
+
+config SOC
+	string
+	default "servant"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 16000000
+
+config RISCV_SOC_INTERRUPT_INIT
+	bool
+	default y
+
+config NUM_IRQS
+	int
+	default 8
+
+config SERV_TIMER
+	bool
+	default y
+
+endif # SOC_RISCV32_SERVANT

zephyr/soc/riscv/servant/Kconfig.soc

@@ -0,0 +1,7 @@
+# Copyright (c) 2020 Olof Kindgren <olof.kindgren@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RISCV32_SERVANT
+	bool "servant SoC"
+	select RISCV
+	select ATOMIC_OPERATIONS_C

zephyr/soc/riscv/servant/irq.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief interrupt management code for riscv SOCs supporting the riscv
+	  privileged architecture specification
+ */
+#include <irq.h>
+
+void arch_irq_enable(unsigned int irq)
+{
+	uint32_t mie;
+
+	/*
+	 * CSR mie register is updated using atomic instruction csrrs
+	 * (atomic read and set bits in CSR register)
+	 */
+	__asm__ volatile ("csrrs %0, mie, %1\n"
+			  : "=r" (mie)
+			  : "r" (1 << irq));
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	uint32_t mie;
+
+	/*
+	 * Use atomic instruction csrrc to disable device interrupt in mie CSR.
+	 * (atomic read and clear bits in CSR register)
+	 */
+	__asm__ volatile ("csrrc %0, mie, %1\n"
+			  : "=r" (mie)
+			  : "r" (1 << irq));
+};
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	uint32_t mie;
+
+	__asm__ volatile ("csrr %0, mie" : "=r" (mie));
+
+	return !!(mie & (1 << irq));
+}
+
+#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
+void soc_interrupt_init(void)
+{
+	/* ensure that all interrupts are disabled */
+	(void)irq_lock();
+
+	__asm__ volatile ("csrwi mie, 0\n"
+			  "csrwi mip, 0\n");
+}
+#endif

zephyr/soc/riscv/servant/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2018 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/riscv/common/linker.ld>

zephyr/soc/riscv/servant/soc.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020 Olof Kindgren <olof.kindgren@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RISCV32_SERVANT_SOC_H_
+#define __RISCV32_SERVANT_SOC_H_
+
+#include <soc_common.h>
+#include <devicetree.h>
+
+/* Bitbang UART configuration */
+#define UART_BITBANG_BASE 0x40000000
+
+/* Timer configuration */
+#define SERV_TIMER_BASE   0x80000000
+#define SERV_TIMER_IRQ    7
+
+/* lib-c hooks required RAM defined variables */
+#define RISCV_RAM_BASE    DT_SRAM_BASE_ADDR_ADDRESS
+#define RISCV_RAM_SIZE    DT_SRAM_SIZE
+
+#endif /* __RISCV32_SERVANT_SOC_H_ */

zephyr/soc/riscv/servant/soc_common.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file configuration macros for riscv SOCs supporting the riscv
+ *       privileged architecture specification
+ */
+
+#ifndef __SOC_COMMON_H_
+#define __SOC_COMMON_H_
+
+/* IRQ numbers */
+#define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
+#define RISCV_MACHINE_TIMER_IRQ      7  /* Machine Timer Interrupt */
+#define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
+
+/* ECALL Exception numbers */
+#define SOC_MCAUSE_ECALL_EXP         11 /* Machine ECALL instruction */
+#define SOC_MCAUSE_USER_ECALL_EXP    8  /* User ECALL instruction */
+
+/* SOC-specific MCAUSE bitfields */
+#ifdef CONFIG_64BIT
+/* Interrupt Mask */
+#define SOC_MCAUSE_IRQ_MASK          (1 << 63)
+/* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFFFFFFFFFF
+#else
+/* Interrupt Mask */
+#define SOC_MCAUSE_IRQ_MASK          (1 << 31)
+/* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFF
+#endif
+
+/* SOC-Specific EXIT ISR command */
+#define SOC_ERET                     mret
+
+#ifndef _ASMLANGUAGE
+
+#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
+void soc_interrupt_init(void);
+#endif
+
+#if defined(CONFIG_RISCV_HAS_PLIC)
+void riscv_plic_irq_enable(uint32_t irq);
+void riscv_plic_irq_disable(uint32_t irq);
+int riscv_plic_irq_is_enabled(uint32_t irq);
+void riscv_plic_set_priority(uint32_t irq, uint32_t priority);
+int riscv_plic_get_irq(void);
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* __SOC_COMMON_H_ */

zephyr/soc/riscv/servant/soc_irq.S

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * common interrupt management code for riscv SOCs supporting the riscv
+ * privileged architecture specification
+ */
+#include <kernel_structs.h>
+#include <offsets.h>
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <soc.h>
+
+/* exports */
+GTEXT(__soc_handle_irq)
+
+/*
+ * SOC-specific function to handle pending IRQ number generating the interrupt.
+ * Exception number is given as parameter via register a0.
+ */
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	/* Clear exception number from CSR mip register */
+	li t1, 1
+	sll t0, t1, a0
+	csrrc t1, mip, t0
+
+	/* Return */
+	jalr x0, ra
+
+/*
+ * __soc_is_irq is defined as .weak to allow re-implementation by
+ * SOCs that does not truly follow the riscv privilege specification.
+ */
+WTEXT(__soc_is_irq)
+
+/*
+ * SOC-specific function to determine if the exception is the result of a
+ * an interrupt or an exception
+ * return 1 (interrupt) or 0 (exception)
+ *
+ */
+SECTION_FUNC(exception.other, __soc_is_irq)
+	/* Read mcause and check if interrupt bit is set */
+	csrr t0, mcause
+	li t1, SOC_MCAUSE_IRQ_MASK
+	and t0, t0, t1
+
+	/* If interrupt bit is not set, return with 0 */
+	addi a0, x0, 0
+	beqz t0, not_interrupt
+	addi a0, a0, 1
+
+not_interrupt:
+	/* return */
+	jalr x0, ra

zephyr/soc/riscv/servant/vector.S

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ * Contributors: 2018 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <toolchain.h>
+
+/* exports */
+GTEXT(__start)
+
+/* imports */
+GTEXT(__initialize)
+GTEXT(__irq_wrapper)
+
+SECTION_FUNC(vectors, __start)
+	.option norvc;
+
+	/*
+	 * Set mtvec (Machine Trap-Vector Base-Address Register)
+	 * to __irq_wrapper.
+	 */
+	la t0, __irq_wrapper
+	csrw mtvec, t0
+
+	/* Jump to __initialize */
+	tail __initialize