Delete trailing whitespace from RTL

rtl/serv_aligner.v

@@ -1,4 +1,4 @@
-module serv_aligner 
+module serv_aligner
    (
     input wire clk,
     input wire rst,
@@ -15,14 +15,14 @@ module serv_aligner
 
     wire [31:0] ibus_rdt_concat;
     wire        ack_en;
-    
+
-    reg  [15:0] lower_hw;    
+    reg  [15:0] lower_hw;
-    reg         ctrl_misal ; 
+    reg         ctrl_misal ;
 
     /* From SERV core to Memory
 
-    o_wb_ibus_adr: Carries address of instruction to memory. In case of misaligned access, 
+    o_wb_ibus_adr: Carries address of instruction to memory. In case of misaligned access,
-    which is caused by pc+2 due to compressed instruction, next instruction is fetched 
+    which is caused by pc+2 due to compressed instruction, next instruction is fetched
     by pc+4 and concatenation is done to make the instruction aligned.
 
     o_wb_ibus_cyc: Simply forwarded from SERV to Memory and is only altered by memory or SERV core.
@@ -43,7 +43,7 @@ module serv_aligner
 
     /* 16-bit register used to hold the upper half word of the current instruction in-case
        concatenation will be required with the upper half word of upcoming instruction
-    */        
+    */
     always @(posedge clk) begin
         if(i_wb_ibus_ack)begin
             lower_hw <= i_wb_ibus_rdt[31:16];
@@ -51,11 +51,11 @@ module serv_aligner
     end
 
     assign ibus_rdt_concat = {i_wb_ibus_rdt[15:0],lower_hw};
-    
+
     /* Two control signals: ack_en, ctrl_misal are set to control the bus transactions between
     SERV core and the memory
     */
-    assign ack_en   = !(i_ibus_adr[1] & !ctrl_misal); 
+    assign ack_en   = !(i_ibus_adr[1] & !ctrl_misal);
 
     always @(posedge clk ) begin
         if(rst)

rtl/serv_bufreg.v

@@ -13,7 +13,7 @@ module serv_bufreg #(
    input wire 	      i_rs1_en,
    input wire 	      i_imm_en,
    input wire 	      i_clr_lsb,
-   input wire 	      i_sh_signed, 
+   input wire 	      i_sh_signed,
    //Data
    input wire 	      i_rs1,
    input wire 	      i_imm,

rtl/serv_compdec.v

@@ -1,13 +1,13 @@
 /* Copyright lowRISC contributors.
 Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
 Licensed under the Apache License, Version 2.0, see LICENSE for details.
-SPDX-License-Identifier: Apache-2.0 
+SPDX-License-Identifier: Apache-2.0
 
 * Adapted to SERV by @Abdulwadoodd as part of the project under spring '22 LFX Mentorship program */
 
 /* Decodes RISC-V compressed instructions into their RV32i equivalent. */
 
-module serv_compdec 
+module serv_compdec
   (
    input wire i_clk,
    input  wire [31:0] i_instr,
@@ -31,7 +31,7 @@ module serv_compdec
 
   always @(posedge i_clk) begin
     if(i_ack)
-      o_iscomp <= !illegal_instr; 
+      o_iscomp <= !illegal_instr;
   end
 
   always @ (*) begin
@@ -71,7 +71,7 @@ module serv_compdec
       end
 
       // C1
- 
+
       // Register address checks for RV32E are performed in the regular instruction decoder.
       // If this check fails, an illegal instruction exception is triggered and the controller
       // writes the actual faulting instruction to mtval.
@@ -228,7 +228,5 @@ module serv_compdec
 
     endcase
   end
-  
+
   endmodule
-
-

rtl/serv_rf_top.v

@@ -6,9 +6,9 @@ module serv_rf_top
         COMPRESSED=0: Disable the compressed decoder and does not allow the misaligned jump of pc
     */
     parameter [0:0] COMPRESSED = 0,
-    /*  
+    /*
-      ALIGN = 1: Fetch the aligned instruction by making two bus transactions if the misaligned address 
+      ALIGN = 1: Fetch the aligned instruction by making two bus transactions if the misaligned address
-      is given to the instruction bus.  
+      is given to the instruction bus.
     */
     parameter [0:0] ALIGN = COMPRESSED,
     /* Multiplication and Division Unit
@@ -68,7 +68,7 @@ module serv_rf_top
    output wire 	      o_dbus_cyc,
    input wire [31:0]  i_dbus_rdt,
    input wire 	      i_dbus_ack,
-   
+
    // Extension
    output wire [31:0] o_ext_rs1,
    output wire [31:0] o_ext_rs2,
@@ -77,7 +77,7 @@ module serv_rf_top
    input  wire        i_ext_ready,
    // MDU
    output wire        o_mdu_valid);
-   
+
    localparam CSR_REGS = WITH_CSR*4;
 
    wire 	      rf_wreq;
@@ -202,7 +202,7 @@ module serv_rf_top
       .o_dbus_cyc   (o_dbus_cyc),
       .i_dbus_rdt   (i_dbus_rdt),
       .i_dbus_ack   (i_dbus_ack),
-      
+
       //Extension
       .o_ext_funct3 (o_ext_funct3),
       .i_ext_ready  (i_ext_ready),