From b0a062ae21be41be1f1bd6f8551e43cb6bda9324 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Wed, 27 Mar 2019 23:16:07 +0100
Subject: [PATCH] Speed up instruction fetching

---
 rtl/serv_ctrl.v | 13 ++++-----
 rtl/serv_top.v  | 76 +++++++++++++++++++++++--------------------------
 2 files changed, 42 insertions(+), 47 deletions(-)

diff --git a/rtl/serv_ctrl.v b/rtl/serv_ctrl.v
index 2462272..0f483ab 100644
--- a/rtl/serv_ctrl.v
+++ b/rtl/serv_ctrl.v
@@ -21,7 +21,7 @@ module serv_ctrl
    output wire 	      o_bad_pc,
    output reg 	      o_misalign = 1'b0,
    output wire [31:0] o_ibus_adr,
-   output reg 	      o_ibus_cyc,
+   output wire	      o_ibus_cyc,
    input wire 	      i_ibus_ack);
 
    parameter RESET_PC = 32'd8;
@@ -85,19 +85,18 @@ module serv_ctrl
 
    wire       pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
 
+   assign o_ibus_cyc = en_pc_r & !i_pc_en;
 
    always @(posedge clk) begin
-      en_pc_r <= i_pc_en;
+      if (i_pc_en)
+	en_pc_r <= 1'b1;
+      else if (o_ibus_cyc & i_ibus_ack)
+        en_pc_r <= 1'b0;
 
       if ((i_cnt[4:2] == 3'd0) & i_cnt_r[1])
 	o_misalign <= pc_plus_offset;
-      if (en_pc_r & !i_pc_en)
-        o_ibus_cyc <= 1'b1;
-      else if (o_ibus_cyc & i_ibus_ack)
-        o_ibus_cyc <= 1'b0;
       if (i_rst) begin
 	 en_pc_r <= 1'b1;
-	 o_ibus_cyc <= 1'b0;
       end
    end
 
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index bdbb53f..8a2ec70 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -338,11 +338,41 @@ module serv_top
       .o_q          (csr_rd));
 
 `ifdef RISCV_FORMAL
-   reg [31:0]    rs1_fv, rs2_fv;
-   reg [31:0]    pc = RESET_PC;
-   reg           ctrl_pc_en_r = 1'b0;
+   reg [31:0] 	 pc = RESET_PC;
 
    always @(posedge clk) begin
+      rvfi_valid <= cnt_done & ctrl_pc_en;
+      rvfi_order <= rvfi_order + rvfi_valid;
+      if (o_ibus_cyc & i_ibus_ack)
+	rvfi_insn <= i_ibus_rdt;
+      if (rd_en)
+        rvfi_rd_wdata <= {rd,rvfi_rd_wdata[31:1]};
+      if (cnt_done & ctrl_pc_en) begin
+         rvfi_pc_rdata <= pc;
+	 if (!rd_en)
+	   rvfi_rd_addr <= 5'd0;
+	 if (!rd_en | !(|rd_addr))
+	   rvfi_rd_wdata <= 32'd0;
+      end
+      rvfi_trap <= trap;
+      if (rvfi_valid) begin
+         rvfi_trap <= 1'b0;
+         pc <= rvfi_pc_wdata;
+      end
+
+      rvfi_halt <= 1'b0;
+      rvfi_intr <= 1'b0;
+      rvfi_mode <= 2'd3;
+      if (rf_ready) begin
+	 rvfi_rs1_addr <= rs1_addr;
+         rvfi_rs2_addr <= rs2_addr;
+	 rvfi_rd_addr  <= rd_addr;
+      end
+      if (rs_en) begin
+         rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]};
+         rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]};
+      end
+
       if (i_dbus_ack) begin
          rvfi_mem_addr <= o_dbus_adr;
          rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel;
@@ -354,44 +384,10 @@ module serv_top
          rvfi_mem_rmask <= 4'b0000;
          rvfi_mem_wmask <= 4'b0000;
       end
-
-      if (i_ibus_ack)
-	rvfi_insn <= i_ibus_rdt;
-
-      ctrl_pc_en_r <= ctrl_pc_en;
-      if (rs_en) begin
-         rs1_fv <= {rs1,rs1_fv[31:1]};
-         rs2_fv <= {rs2,rs2_fv[31:1]};
-      end
-      if (rd_en) begin
-         rvfi_rd_wdata <= {rd & (|rd_addr),rvfi_rd_wdata[31:1]};
-         rvfi_rd_addr <= rd_addr;
-      end else if (i_ibus_ack) begin
-	 rvfi_rd_wdata <= 32'd0;
-	 rvfi_rd_addr  <= 5'd0;
-      end
-
-      if (trap)
-	rvfi_trap <= 1'b1;
-      else if (i_ibus_ack)
-	rvfi_trap <= 1'b0;
-
-      rvfi_valid <= 1'b0;
-      if (ctrl_pc_en_r & !ctrl_pc_en) begin
-         pc <= o_ibus_adr;
-         rvfi_valid <= 1'b1;
-         rvfi_order <= rvfi_order + 1;
-         rvfi_halt <= 1'b0;
-         rvfi_intr <= 1'b0;
-         rvfi_mode <= 2'd3;
-         rvfi_rs1_addr <= rs1_addr;
-         rvfi_rs2_addr <= rs2_addr;
-         rvfi_rs1_rdata <= rs1_fv;
-         rvfi_rs2_rdata <= rs2_fv;
-         rvfi_pc_rdata <= pc;
-         rvfi_pc_wdata <= o_ibus_adr;
-      end
    end
+   always @(o_ibus_adr)
+     rvfi_pc_wdata <= o_ibus_adr;
+
 `endif
 
 endmodule