diff --git a/west.yml b/west.yml
index 1407f41..1f14b1a 100644
--- a/west.yml
+++ b/west.yml
@@ -5,5 +5,5 @@ manifest:
   projects:
     - name: zephyr
       remote: zephyrproject-rtos
-      revision: v2.4.0
+      revision: v3.5.0
       import: true
diff --git a/zephyr/boards/riscv/service/service.dts b/zephyr/boards/riscv/service/service.dts
index 840979d..34dcde3 100644
--- a/zephyr/boards/riscv/service/service.dts
+++ b/zephyr/boards/riscv/service/service.dts
@@ -11,11 +11,23 @@
 / {
 	chosen {
 		zephyr,sram = &ram;
+		zephyr,console = &uart0;
 	};
 
 	ram: memory@0 {
 		compatible = "mmio-sram";
 		reg = <0x0 0x8000>;
 	};
+
+	soc {
+		compatible = "olofk,serv";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial@0 {
+			reg = <0x0 0x1>;
+			compatible = "olofk,serial";
+		};
+	};
 };
 
diff --git a/zephyr/boards/riscv/service/service.yaml b/zephyr/boards/riscv/service/service.yaml
index a815d23..e5cd539 100644
--- a/zephyr/boards/riscv/service/service.yaml
+++ b/zephyr/boards/riscv/service/service.yaml
@@ -9,6 +9,7 @@ arch: riscv32
 toolchain:
   - zephyr
 ram: 32
+vendor: olofk
 testing:
   ignore_tags:
     - net
diff --git a/zephyr/boards/riscv/service/service_defconfig b/zephyr/boards/riscv/service/service_defconfig
index e8bedf2..a38551c 100644
--- a/zephyr/boards/riscv/service/service_defconfig
+++ b/zephyr/boards/riscv/service/service_defconfig
@@ -8,6 +8,5 @@ CONFIG_SERIAL=y
 CONFIG_UART_BITBANG=y
 
 CONFIG_UART_CONSOLE=y
-CONFIG_UART_CONSOLE_ON_DEV_NAME="uart0"
 
 CONFIG_XIP=n
diff --git a/zephyr/drivers/serial/uart_bitbang.c b/zephyr/drivers/serial/uart_bitbang.c
index d2b4ef1..1d606cb 100644
--- a/zephyr/drivers/serial/uart_bitbang.c
+++ b/zephyr/drivers/serial/uart_bitbang.c
@@ -4,9 +4,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <kernel.h>
-#include <arch/cpu.h>
-#include <drivers/uart.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/uart.h>
+
+#define DT_DRV_COMPAT olofk_serial
 
 #define reg_uart_data (*(volatile uint32_t*)UART_BITBANG_BASE)
 
@@ -50,8 +53,25 @@ static const struct uart_driver_api uart_bitbang_driver_api = {
 	.err_check        = NULL,
 };
 
+struct my_dev_data {
 
-DEVICE_AND_API_INIT(uart_bitbang, "uart0", &uart_bitbang_init,
-		    NULL, NULL,
-		    PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
-		    &uart_bitbang_driver_api);
+};
+
+struct my_dev_cfg {
+
+};
+
+#define CREATE_MY_DEVICE(inst)                                       \
+     static struct my_dev_data my_data_##inst = {                    \
+     };                                                              \
+     static const struct my_dev_cfg my_cfg_##inst = {                \
+     };                                                              \
+     DEVICE_DT_INST_DEFINE(inst,                                     \
+                           uart_bitbang_init,                        \
+                           NULL,                                     \
+                           &my_data_##inst,                          \
+                           &my_cfg_##inst,                           \
+                           PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,  \
+                           &uart_bitbang_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(CREATE_MY_DEVICE)
diff --git a/zephyr/drivers/timer/serv_timer.c b/zephyr/drivers/timer/serv_timer.c
index 0eec6ee..d48b771 100644
--- a/zephyr/drivers/timer/serv_timer.c
+++ b/zephyr/drivers/timer/serv_timer.c
@@ -7,9 +7,10 @@
 /*
   This is basically a 32-bit version of riscv_machine_timer.c for Zephyr
 */
-#include <drivers/timer/system_timer.h>
-#include <sys_clock.h>
-#include <spinlock.h>
+#include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/device.h>
 #include <soc.h>
 
 #define CYC_PER_TICK ((uint32_t)((uint32_t)sys_clock_hw_cycles_per_sec()	\
@@ -53,20 +54,19 @@ static void timer_isr(void *arg)
 	}
 
 	k_spin_unlock(&lock, key);
-	z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
+	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
 }
 
-int z_clock_driver_init(const struct device *device)
+int sys_clock_driver_init()
 {
-	ARG_UNUSED(device);
-
 	IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
-	set_mtimecmp(mtime() + (uint32_t)CYC_PER_TICK);
+	last_count = mtime();
+	set_mtimecmp(last_count + (uint32_t)CYC_PER_TICK);
 	irq_enable(RISCV_MACHINE_TIMER_IRQ);
 	return 0;
 }
 
-void z_clock_set_timeout(int32_t ticks, bool idle)
+void sys_clock_set_timeout(int32_t ticks, bool idle)
 {
 	ARG_UNUSED(idle);
 
@@ -106,7 +106,7 @@ void z_clock_set_timeout(int32_t ticks, bool idle)
 #endif
 }
 
-uint32_t z_clock_elapsed(void)
+uint32_t sys_clock_elapsed(void)
 {
 	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
 		return 0;
@@ -119,7 +119,10 @@ uint32_t z_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_timer_cycle_get_32(void)
 {
 	return mtime();
 }
+
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
+	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/zephyr/dts/riscv/serv.dtsi b/zephyr/dts/riscv/serv.dtsi
index e92b8d7..f33dc7a 100644
--- a/zephyr/dts/riscv/serv.dtsi
+++ b/zephyr/dts/riscv/serv.dtsi
@@ -8,4 +8,16 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 	compatible = "olofk,servant";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "olofk,serv";
+			riscv,isa = "rv32i_zicsr";
+			reg = <0>;
+			device_type = "cpu";
+		};
+	};
 };
diff --git a/zephyr/soc/riscv/servant/Kconfig.soc b/zephyr/soc/riscv/servant/Kconfig.soc
index 2aa0577..932055c 100644
--- a/zephyr/soc/riscv/servant/Kconfig.soc
+++ b/zephyr/soc/riscv/servant/Kconfig.soc
@@ -5,3 +5,4 @@ config SOC_RISCV32_SERVANT
 	bool "servant SoC"
 	select RISCV
 	select ATOMIC_OPERATIONS_C
+	select RISCV_ISA_EXT_ZICSR
diff --git a/zephyr/soc/riscv/servant/irq.c b/zephyr/soc/riscv/servant/irq.c
index a57d647..61a343f 100644
--- a/zephyr/soc/riscv/servant/irq.c
+++ b/zephyr/soc/riscv/servant/irq.c
@@ -9,7 +9,7 @@
  * @brief interrupt management code for riscv SOCs supporting the riscv
 	  privileged architecture specification
  */
-#include <irq.h>
+#include <zephyr/irq.h>
 
 void arch_irq_enable(unsigned int irq)
 {
diff --git a/zephyr/soc/riscv/servant/linker.ld b/zephyr/soc/riscv/servant/linker.ld
index 85e1212..0d220a2 100644
--- a/zephyr/soc/riscv/servant/linker.ld
+++ b/zephyr/soc/riscv/servant/linker.ld
@@ -4,4 +4,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/riscv/common/linker.ld>
+#include <zephyr/arch/riscv/common/linker.ld>
diff --git a/zephyr/soc/riscv/servant/soc.h b/zephyr/soc/riscv/servant/soc.h
index 0780bb5..58ff95b 100644
--- a/zephyr/soc/riscv/servant/soc.h
+++ b/zephyr/soc/riscv/servant/soc.h
@@ -8,7 +8,6 @@
 #define __RISCV32_SERVANT_SOC_H_
 
 #include <soc_common.h>
-#include <devicetree.h>
 
 /* Bitbang UART configuration */
 #define UART_BITBANG_BASE 0x40000000
@@ -17,8 +16,4 @@
 #define SERV_TIMER_BASE   0x80000000
 #define SERV_TIMER_IRQ    7
 
-/* lib-c hooks required RAM defined variables */
-#define RISCV_RAM_BASE    DT_SRAM_BASE_ADDR_ADDRESS
-#define RISCV_RAM_SIZE    DT_SRAM_SIZE
-
 #endif /* __RISCV32_SERVANT_SOC_H_ */
diff --git a/zephyr/soc/riscv/servant/soc_irq.S b/zephyr/soc/riscv/servant/soc_irq.S
index 3a8904d..bbaef8c 100644
--- a/zephyr/soc/riscv/servant/soc_irq.S
+++ b/zephyr/soc/riscv/servant/soc_irq.S
@@ -8,10 +8,8 @@
  * common interrupt management code for riscv SOCs supporting the riscv
  * privileged architecture specification
  */
-#include <kernel_structs.h>
 #include <offsets.h>
-#include <toolchain.h>
-#include <linker/sections.h>
+#include <zephyr/linker/sections.h>
 #include <soc.h>
 
 /* exports */
diff --git a/zephyr/soc/riscv/servant/vector.S b/zephyr/soc/riscv/servant/vector.S
index a6decc5..3fa9897 100644
--- a/zephyr/soc/riscv/servant/vector.S
+++ b/zephyr/soc/riscv/servant/vector.S
@@ -5,23 +5,23 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <toolchain.h>
+#include <zephyr/toolchain.h>
 
 /* exports */
 GTEXT(__start)
 
 /* imports */
 GTEXT(__initialize)
-GTEXT(__irq_wrapper)
+GTEXT(_isr_wrapper)
 
 SECTION_FUNC(vectors, __start)
 	.option norvc;
 
 	/*
 	 * Set mtvec (Machine Trap-Vector Base-Address Register)
-	 * to __irq_wrapper.
+	 * to __isr_wrapper.
 	 */
-	la t0, __irq_wrapper
+	la t0, _isr_wrapper
 	csrw mtvec, t0
 
 	/* Jump to __initialize */